northbridge/intel/gm45: transation away from device_t
Replace the use of the old device_t definition inside northbridge/intel/gm45. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I87754799f922cf241fb456071bac04e6fe1eab34 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16402 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -19,7 +19,7 @@
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void gm45_early_init(void)
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{
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const device_t d0f0 = PCI_DEV(0, 0, 0);
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const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0);
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/* Setup MCHBAR. */
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pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1);
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@ -434,7 +434,7 @@ u32 decode_igd_gtt_size(u32 gsm);
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void init_iommu(void);
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#if ENV_RAMSTAGE
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#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__)
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#include <device/device.h>
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struct acpi_rsdp;
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@ -30,9 +30,9 @@
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/* The PEG settings have to be set before ASPM is setup on DMI. */
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static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg)
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{
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const device_t mch_dev = PCI_DEV(0, 0, 0);
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const device_t peg_dev = PCI_DEV(0, 1, 0);
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const device_t igd_dev = PCI_DEV(0, 2, 0);
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const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);
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const pci_devfn_t peg_dev = PCI_DEV(0, 1, 0);
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const pci_devfn_t igd_dev = PCI_DEV(0, 2, 0);
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u16 reg16;
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u32 reg32;
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@ -110,7 +110,7 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg)
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static void disable_igd(const sysinfo_t *const sysinfo)
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{
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const device_t mch_dev = PCI_DEV(0, 0, 0);
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const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);
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printk(BIOS_DEBUG, "Disabling IGD.\n");
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@ -131,7 +131,7 @@ static void disable_igd(const sysinfo_t *const sysinfo)
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void init_igd(const sysinfo_t *const sysinfo)
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{
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const device_t mch_dev = PCI_DEV(0, 0, 0);
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const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);
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const u8 capid = pci_read_config8(mch_dev, D0F0_CAPID0 + 4);
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if (!sysinfo->enable_igd || (capid & (1 << (33 - 32))))
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@ -142,7 +142,7 @@ void init_igd(const sysinfo_t *const sysinfo)
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void igd_compute_ggc(sysinfo_t *const sysinfo)
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{
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const device_t mch_dev = PCI_DEV(0, 0, 0);
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const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);
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const u32 capid = pci_read_config32(mch_dev, D0F0_CAPID0 + 4);
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if (!sysinfo->enable_igd || (capid & (1 << (33 - 32))))
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@ -48,7 +48,7 @@ void init_iommu()
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/* clear GTT */
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u32 gtt = pci_read_config16(PCI_DEV(0, 0, 0), 0x52);
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if (gtt & 0x400) { /* VT mode */
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device_t igd = PCI_DEV(0, 2, 0);
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pci_devfn_t igd = PCI_DEV(0, 2, 0);
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/* setup somewhere */
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u8 cmd = pci_read_config8(igd, PCI_COMMAND);
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@ -67,7 +67,7 @@ void init_iommu()
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if (stepping == STEPPING_B3) {
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MCHBAR8(0xffc) |= 1 << 4;
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device_t peg = PCI_DEV(0, 1, 0);
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pci_devfn_t peg = PCI_DEV(0, 1, 0);
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/* FIXME: proper test? */
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if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff) {
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int val = pci_read_config32(peg, 0xfc) | (1 << 15);
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@ -112,8 +112,8 @@ static void init_pcie(const int peg_enabled,
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u8 tmp8;
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u16 tmp16;
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u32 tmp;
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const device_t mch = PCI_DEV(0, 0, 0);
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const device_t pciex = PCI_DEV(0, 1, 0);
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const pci_devfn_t mch = PCI_DEV(0, 0, 0);
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const pci_devfn_t pciex = PCI_DEV(0, 1, 0);
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printk(BIOS_DEBUG, "PEG x%d %s, SDVO %s\n", peg_x16?16:1,
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peg_enabled?"enabled":"disabled",
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@ -162,7 +162,7 @@ static void init_pcie(const int peg_enabled,
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static void setup_aspm(const stepping_t stepping, const int peg_enabled)
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{
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u32 tmp32;
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const device_t pciex = PCI_DEV(0, 1, 0);
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const pci_devfn_t pciex = PCI_DEV(0, 1, 0);
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/* Prerequisites for ASPM: */
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if (peg_enabled) {
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@ -327,7 +327,7 @@ static void setup_rcrb(const int peg_enabled)
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void gm45_late_init(const stepping_t stepping)
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{
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const device_t mch = PCI_DEV(0, 0, 0);
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const pci_devfn_t mch = PCI_DEV(0, 0, 0);
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const int peg_enabled = (pci_read_config8(mch, D0F0_DEVEN) >> 1) & 1;
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const int sdvo_enabled = (MCHBAR16(0x40) >> 8) & 1;
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const int peg_x16 = (peg_enabled && !sdvo_enabled);
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