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northbridge/intel/gm45: transation away from device_t 

Replace the use of the old device_t definition inside
northbridge/intel/gm45.

The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.

Change-Id: I87754799f922cf241fb456071bac04e6fe1eab34
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16402
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Furquan Shaikh 2016-08-29 22:51:41 -07:00 committed by Martin Roth
parent 823f1a9bbf
commit 25f75b28e4
5 changed files with 14 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/northbridge/intel/gm45/early_init.c
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@ -19,7 +19,7 @@
void gm45_early_init(void) void gm45_early_init(void)
{ {
const device_t d0f0 = PCI_DEV(0, 0, 0); const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0);
/* Setup MCHBAR. */ /* Setup MCHBAR. */
pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1); pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1);

2
src/northbridge/intel/gm45/gm45.h
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@ -434,7 +434,7 @@ u32 decode_igd_gtt_size(u32 gsm);
void init_iommu(void); void init_iommu(void);
#if ENV_RAMSTAGE #if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__)
#include <device/device.h> #include <device/device.h>
struct acpi_rsdp; struct acpi_rsdp;

12
src/northbridge/intel/gm45/igd.c
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@ -30,9 +30,9 @@
/* The PEG settings have to be set before ASPM is setup on DMI. */ /* The PEG settings have to be set before ASPM is setup on DMI. */
static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg) static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg)
{ {
const device_t mch_dev = PCI_DEV(0, 0, 0); const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);
const device_t peg_dev = PCI_DEV(0, 1, 0); const pci_devfn_t peg_dev = PCI_DEV(0, 1, 0);
const device_t igd_dev = PCI_DEV(0, 2, 0); const pci_devfn_t igd_dev = PCI_DEV(0, 2, 0);
u16 reg16; u16 reg16;
u32 reg32; u32 reg32;
@ -110,7 +110,7 @@ static void enable_igd(const sysinfo_t *const sysinfo, const int no_peg)
static void disable_igd(const sysinfo_t *const sysinfo) static void disable_igd(const sysinfo_t *const sysinfo)
{ {
const device_t mch_dev = PCI_DEV(0, 0, 0); const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);
printk(BIOS_DEBUG, "Disabling IGD.\n"); printk(BIOS_DEBUG, "Disabling IGD.\n");
@ -131,7 +131,7 @@ static void disable_igd(const sysinfo_t *const sysinfo)
void init_igd(const sysinfo_t *const sysinfo) void init_igd(const sysinfo_t *const sysinfo)
{ {
const device_t mch_dev = PCI_DEV(0, 0, 0); const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);
const u8 capid = pci_read_config8(mch_dev, D0F0_CAPID0 + 4); const u8 capid = pci_read_config8(mch_dev, D0F0_CAPID0 + 4);
if (!sysinfo->enable_igd || (capid & (1 << (33 - 32)))) if (!sysinfo->enable_igd || (capid & (1 << (33 - 32))))
@ -142,7 +142,7 @@ void init_igd(const sysinfo_t *const sysinfo)
void igd_compute_ggc(sysinfo_t *const sysinfo) void igd_compute_ggc(sysinfo_t *const sysinfo)
{ {
const device_t mch_dev = PCI_DEV(0, 0, 0); const pci_devfn_t mch_dev = PCI_DEV(0, 0, 0);
const u32 capid = pci_read_config32(mch_dev, D0F0_CAPID0 + 4); const u32 capid = pci_read_config32(mch_dev, D0F0_CAPID0 + 4);
if (!sysinfo->enable_igd || (capid & (1 << (33 - 32)))) if (!sysinfo->enable_igd || (capid & (1 << (33 - 32))))

4
src/northbridge/intel/gm45/iommu.c
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@ -48,7 +48,7 @@ void init_iommu()
/* clear GTT */ /* clear GTT */
u32 gtt = pci_read_config16(PCI_DEV(0, 0, 0), 0x52); u32 gtt = pci_read_config16(PCI_DEV(0, 0, 0), 0x52);
if (gtt & 0x400) { /* VT mode */ if (gtt & 0x400) { /* VT mode */
device_t igd = PCI_DEV(0, 2, 0); pci_devfn_t igd = PCI_DEV(0, 2, 0);
/* setup somewhere */ /* setup somewhere */
u8 cmd = pci_read_config8(igd, PCI_COMMAND); u8 cmd = pci_read_config8(igd, PCI_COMMAND);
@ -67,7 +67,7 @@ void init_iommu()
if (stepping == STEPPING_B3) { if (stepping == STEPPING_B3) {
MCHBAR8(0xffc) |= 1 << 4; MCHBAR8(0xffc) |= 1 << 4;
device_t peg = PCI_DEV(0, 1, 0); pci_devfn_t peg = PCI_DEV(0, 1, 0);
/* FIXME: proper test? */ /* FIXME: proper test? */
if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff) { if (pci_read_config8(peg, PCI_CLASS_REVISION) != 0xff) {
int val = pci_read_config32(peg, 0xfc) | (1 << 15); int val = pci_read_config32(peg, 0xfc) | (1 << 15);

8
src/northbridge/intel/gm45/pcie.c
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@ -112,8 +112,8 @@ static void init_pcie(const int peg_enabled,
u8 tmp8; u8 tmp8;
u16 tmp16; u16 tmp16;
u32 tmp; u32 tmp;
const device_t mch = PCI_DEV(0, 0, 0); const pci_devfn_t mch = PCI_DEV(0, 0, 0);
const device_t pciex = PCI_DEV(0, 1, 0); const pci_devfn_t pciex = PCI_DEV(0, 1, 0);
printk(BIOS_DEBUG, "PEG x%d %s, SDVO %s\n", peg_x16?16:1, printk(BIOS_DEBUG, "PEG x%d %s, SDVO %s\n", peg_x16?16:1,
peg_enabled?"enabled":"disabled", peg_enabled?"enabled":"disabled",
@ -162,7 +162,7 @@ static void init_pcie(const int peg_enabled,
static void setup_aspm(const stepping_t stepping, const int peg_enabled) static void setup_aspm(const stepping_t stepping, const int peg_enabled)
{ {
u32 tmp32; u32 tmp32;
const device_t pciex = PCI_DEV(0, 1, 0); const pci_devfn_t pciex = PCI_DEV(0, 1, 0);
/* Prerequisites for ASPM: */ /* Prerequisites for ASPM: */
if (peg_enabled) { if (peg_enabled) {
@ -327,7 +327,7 @@ static void setup_rcrb(const int peg_enabled)
void gm45_late_init(const stepping_t stepping) void gm45_late_init(const stepping_t stepping)
{ {
const device_t mch = PCI_DEV(0, 0, 0); const pci_devfn_t mch = PCI_DEV(0, 0, 0);
const int peg_enabled = (pci_read_config8(mch, D0F0_DEVEN) >> 1) & 1; const int peg_enabled = (pci_read_config8(mch, D0F0_DEVEN) >> 1) & 1;
const int sdvo_enabled = (MCHBAR16(0x40) >> 8) & 1; const int sdvo_enabled = (MCHBAR16(0x40) >> 8) & 1;
const int peg_x16 = (peg_enabled && !sdvo_enabled); const int peg_x16 = (peg_enabled && !sdvo_enabled);