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cezanne/psp_verstage: add reset/timer svc 

The new cezanne PSP release added support for these svcs. So add those
functionality back to cezanne psp_verstage.

BUG=b:187906425

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Id542f5ed0762f582ea966466d67ed938ecb9c1f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Kangheui Won 2021-05-14 15:17:50 +10:00 committed by Werner Zeh
parent 32f43e0e13
commit 260f0f93ef
4 changed files with 55 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/soc/amd/cezanne/psp_verstage/chipset.c
View File

@ -8,8 +8,6 @@
#include <bl_uapp/bl_syscall_public.h>
#include <console/console.h>
#include <psp_verstage.h>
#include <reset.h>
#include <timer.h>
uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset)
{
@ -35,17 +33,3 @@ uint32_t svc_write_postcode(uint32_t postcode)
{
return 0;
}
static uint64_t tmp_timer_value = 0;
void timer_monotonic_get(struct mono_time *mt)
{
mt->microseconds = tmp_timer_value / 1000;
tmp_timer_value++;
}
void do_board_reset(void)
{
printk(BIOS_ERR, "Reset not implemented yet.\n");
while (1)
;
}

21
src/soc/amd/cezanne/psp_verstage/svc.c
View File

@ -35,9 +35,8 @@ uint32_t svc_get_boot_mode(uint32_t *boot_mode)
void svc_delay_in_usec(uint32_t delay)
{
uint32_t i;
for (i = 0; i < delay * 1000; i++)
asm volatile ("nop");
uint32_t unused = 0;
SVC_CALL1(SVC_DELAY_IN_MICRO_SECONDS, delay, unused);
}
uint32_t svc_get_spi_rom_info(struct spirom_info *spi_rom_info)
@ -97,3 +96,19 @@ uint32_t svc_save_uapp_data(void *address, uint32_t size)
SVC_CALL2(SVC_COPY_DATA_FROM_UAPP, (uint32_t)address, size, retval);
return retval;
}
uint32_t svc_read_timer_val(enum psp_timer_type type, uint64_t *counter_value)
{
unsigned int retval = 0;
assert(type < PSP_TIMER_TYPE_MAX);
SVC_CALL2(SVC_READ_TIMER_VAL, type, counter_value, retval);
return retval;
}
uint32_t svc_reset_system(enum reset_type reset_type)
{
unsigned int retval = 0;
assert(reset_type < RESET_TYPE_MAX);
SVC_CALL1(SVC_RESET_SYSTEM, reset_type, retval);
return retval;
}

4
src/soc/amd/common/psp_verstage/Makefile.inc
View File

@ -14,10 +14,10 @@ verstage-y += post.c
verstage-y += printk.c
verstage-y += psp_verstage.c
verstage-y += psp.c
ifneq ($(CONFIG_SOC_AMD_CEZANNE),y)
# cezanne PSP does not support these functions yet (b/187906425)
verstage-y += reset.c
verstage-y += timer.c
ifneq ($(CONFIG_SOC_AMD_CEZANNE),y)
# cezanne PSP does not support these functions yet (b/187906425)
verstage-y += vboot_crypto.c
endif

35
src/vendorcode/amd/fsp/cezanne/include/bl_uapp/bl_syscall_public.h
View File

@ -37,6 +37,7 @@
#define SVC_DEBUG_PRINT 0x06
#define SVC_DEBUG_PRINT_EX 0x1A
#define SVC_GET_BOOT_MODE 0x1C
#define SVC_DELAY_IN_MICRO_SECONDS 0x2F
#define SVC_GET_SPI_INFO 0x60
#define SVC_MAP_SPIROM_DEVICE 0x61
#define SVC_UNMAP_SPIROM_DEVICE 0x62
@ -44,6 +45,8 @@
#define SVC_UNMAP_FCH_IO_DEVICE 0x64
#define SVC_UPDATE_PSP_BIOS_DIR 0x65
#define SVC_COPY_DATA_FROM_UAPP 0x66
#define SVC_RESET_SYSTEM 0x67
#define SVC_READ_TIMER_VAL 0x68
enum psp_boot_mode {
PSP_BOOT_MODE_S0 = 0x0,
@ -54,6 +57,13 @@ enum psp_boot_mode {
PSP_BOOT_MODE_S5_WARM = 0x5,
};
enum reset_type
{
RESET_TYPE_COLD = 0,
RESET_TYPE_WARM = 1,
RESET_TYPE_MAX = 2,
};
enum fch_io_device {
FCH_IO_DEVICE_SPI,
FCH_IO_DEVICE_I2C,
@ -81,6 +91,12 @@ struct spirom_info {
uint32_t SpiBiosSize;
};
enum psp_timer_type {
PSP_TIMER_TYPE_CHRONO = 0,
PSP_TIMER_TYPE_SECURE_RTC = 1,
PSP_TIMER_TYPE_MAX = 2,
};
/*
* Exit to the main Boot Loader. This does not return back to user application.
*
@ -205,6 +221,25 @@ uint32_t svc_update_psp_bios_dir(uint32_t *psp_dir_offset,
*/
uint32_t svc_save_uapp_data(void *address, uint32_t size);
/*
* Read timer raw (currently CHRONO and RTC) value
*
* Parameters:
* type - [in] Type of timer UAPP would like to read from
* (currently CHRONO and RTC)
* counter_value - [out] return the raw counter value read from
* RTC or CHRONO_LO/HI counter register
-----------------------------------------------------------------------------*/
uint32_t svc_read_timer_val(enum psp_timer_type type, uint64_t *counter_value);
/*
* Reset the system
*
* Parameters:
* reset_type - Cold or Warm reset
*/
uint32_t svc_reset_system(enum reset_type reset_type);
/*
* Write postcode to Port-80
*