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mb/google: Drop unneeded empty lines

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Change-Id: I4151d1a6ce94763432f307fbc8bc4afe229856ea
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Elyes HAOUAS 2020-09-10 11:34:54 +02:00 committed by Michael Niewöhner
parent ca36aedb4e
commit 261226dd42
69 changed files with 0 additions and 122 deletions
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1
src/mainboard/google/auron/mainboard.c
View file

@ -5,7 +5,6 @@
#include "ec.h"
#include "variant.h"
__weak void lan_init(void)
{
}

1
src/mainboard/google/auron/variants/lulu/spd/spd.c
View file

@ -104,7 +104,6 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
if (spd_file_len < SPD_LEN)
die("Missing SPD data.");
/* CH0 */
memcpy(pei_data->spd_data[0][0],
spd_file + (spd_index * SPD_LEN), SPD_LEN);

2
src/mainboard/google/beltino/mainboard.c
View file

@ -14,8 +14,6 @@ void mainboard_suspend_resume(void)
apm_control(APM_CNT_FINALIZE);
}
static void mainboard_init(struct device *dev)
{
lan_init();

1
src/mainboard/google/butterfly/acpi_tables.c
View file

@ -15,7 +15,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
// TODO: MLR
// The firmware read/write status is a "virtual" switch and
// will be handled elsewhere. Until then hard-code to

1
src/mainboard/google/butterfly/mainboard.c
View file

@ -153,7 +153,6 @@ static void program_keyboard_type(u32 search_address, u32 search_length)
} else
printk(BIOS_DEBUG, "Error: Could not locate VPD area\n");
printk(BIOS_DEBUG, "Setting Keyboard type in EC to ");
printk(BIOS_DEBUG, (kbd_type == EC_KBD_JP) ? "Japanese" : "English");
printk(BIOS_DEBUG, ".\n");

1
src/mainboard/google/cyan/acpi/codec_maxim.asl
View file

@ -88,7 +88,6 @@ Scope (\_SB.PCI0.I2C2)
}
}
Scope (\_SB.PCI0.LPEA)
{
Name (GBUF, ResourceTemplate ()

1
src/mainboard/google/cyan/mainboard.c
View file

@ -19,7 +19,6 @@ static void mainboard_enable(struct device *dev)
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

4
src/mainboard/google/cyan/variants/banon/gpio.c
View file

@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_END
};
/* South West Community */
static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_NC, /* 00 FST_SPI_D2 */
@ -129,7 +128,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_END
};
/* North Community */
static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 00 GPIO_DFX0 */
@ -199,7 +197,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_END
};
/* East Community */
static const struct soc_gpio_map gpe_gpio_map[] = {
Native_M1, /* 00 PMU_SLP_S3_B */
@ -229,7 +226,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = {
GPIO_END
};
static struct soc_gpio_config gpio_config = {
/* BSW */
.north = gpn_gpio_map,

2
src/mainboard/google/cyan/variants/banon/include/variant/acpi/dptf.asl
View file

@ -5,7 +5,6 @@
#define DPTF_TSR0_PASSIVE 46
#define DPTF_TSR0_CRITICAL 60
#define DPTF_TSR1_SENSOR_ID 1
#define DPTF_TSR1_SENSOR_NAME "TMP432_CPU_bottom"
#define DPTF_TSR1_PASSIVE 48
@ -16,7 +15,6 @@
#define DPTF_TSR2_PASSIVE 68
#define DPTF_TSR2_CRITICAL 80
#define DPTF_ENABLE_CHARGER
/* Charger performance states, board-specific values from charger and EC */

4
src/mainboard/google/cyan/variants/celes/gpio.c
View file

@ -66,7 +66,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_END
};
/* South West Community */
static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_NC, /* 00 FST_SPI_D2 */
@ -132,7 +131,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_END
};
/* North Community */
static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 00 GPIO_DFX0 */
@ -202,7 +200,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_END
};
/* East Community */
static const struct soc_gpio_map gpe_gpio_map[] = {
Native_M1, /* 00 PMU_SLP_S3_B */
@ -232,7 +229,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = {
GPIO_END
};
static struct soc_gpio_config gpio_config = {
/* BSW */
.north = gpn_gpio_map,

4
src/mainboard/google/cyan/variants/cyan/gpio.c
View file

@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_END
};
/* South West Community */
static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_NC, /* 00 FST_SPI_D2 */
@ -132,7 +131,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_END
};
/* North Community */
static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 00 GPIO_DFX0 */
@ -202,7 +200,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_END
};
/* East Community */
static const struct soc_gpio_map gpe_gpio_map[] = {
Native_M1, /* 00 PMU_SLP_S3_B */
@ -232,7 +229,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = {
GPIO_END
};
static struct soc_gpio_config gpio_config = {
/* BSW */
.north = gpn_gpio_map,

1
src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h
View file

@ -39,7 +39,6 @@
#define BOARD_TOUCHSCREEN_I2C_BUS 0
#define BOARD_TOUCHSCREEN_I2C_ADDR 0x10
/* SD CARD gpio */
#define SDCARD_CD 81

4
src/mainboard/google/cyan/variants/edgar/gpio.c
View file

@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_END
};
/* South West Community */
static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_NC, /* 00 FST_SPI_D2 */
@ -129,7 +128,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_END
};
/* North Community */
static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 00 GPIO_DFX0 */
@ -197,7 +195,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_END
};
/* East Community */
static const struct soc_gpio_map gpe_gpio_map[] = {
Native_M1, /* 00 PMU_SLP_S3_B */
@ -227,7 +224,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = {
GPIO_END
};
static struct soc_gpio_config gpio_config = {
/* BSW */
.north = gpn_gpio_map,

2
src/mainboard/google/cyan/variants/edgar/include/variant/acpi/dptf.asl
View file

@ -5,7 +5,6 @@
#define DPTF_TSR0_PASSIVE 45
#define DPTF_TSR0_CRITICAL 75
#define DPTF_TSR1_SENSOR_ID 2
#define DPTF_TSR1_SENSOR_NAME "R4303_CPU"
#define DPTF_TSR1_PASSIVE 49
@ -16,7 +15,6 @@
#define DPTF_TSR2_PASSIVE 49
#define DPTF_TSR2_CRITICAL 70
#define DPTF_ENABLE_CHARGER
/* Charger performance states, board-specific values from charger and EC */

4
src/mainboard/google/cyan/variants/kefka/gpio.c
View file

@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_END
};
/* South West Community */
static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_NC, /* 00 FST_SPI_D2 */
@ -128,7 +127,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_END
};
/* North Community */
static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 00 GPIO_DFX0 */
@ -197,7 +195,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_END
};
/* East Community */
static const struct soc_gpio_map gpe_gpio_map[] = {
Native_M1, /* 00 PMU_SLP_S3_B */
@ -227,7 +224,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = {
GPIO_END
};
static struct soc_gpio_config gpio_config = {
/* BSW */
.north = gpn_gpio_map,

2
src/mainboard/google/cyan/variants/kefka/include/variant/acpi/dptf.asl
View file

@ -5,7 +5,6 @@
#define DPTF_TSR0_PASSIVE 55
#define DPTF_TSR0_CRITICAL 68
#define DPTF_TSR1_SENSOR_ID 1
#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
#define DPTF_TSR1_PASSIVE 55
@ -16,7 +15,6 @@
#define DPTF_TSR2_PASSIVE 53
#define DPTF_TSR2_CRITICAL 66
#define DPTF_ENABLE_CHARGER
/* Charger performance states, board-specific values from charger and EC */

4
src/mainboard/google/cyan/variants/reks/gpio.c
View file

@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_END
};
/* South West Community */
static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_NC, /* 00 FST_SPI_D2 */
@ -131,7 +130,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_END
};
/* North Community */
static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 00 GPIO_DFX0 */
@ -201,7 +199,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_END
};
/* East Community */
static const struct soc_gpio_map gpe_gpio_map[] = {
Native_M1, /* 00 PMU_SLP_S3_B */
@ -231,7 +228,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = {
GPIO_END
};
static struct soc_gpio_config gpio_config = {
/* BSW */
.north = gpn_gpio_map,

2
src/mainboard/google/cyan/variants/reks/include/variant/acpi/dptf.asl
View file

@ -5,7 +5,6 @@
#define DPTF_TSR0_PASSIVE 49
#define DPTF_TSR0_CRITICAL 70
#define DPTF_TSR1_SENSOR_ID 1
#define DPTF_TSR1_SENSOR_NAME "TMP432_Charger"
#define DPTF_TSR1_PASSIVE 65
@ -16,7 +15,6 @@
#define DPTF_TSR2_PASSIVE 48
#define DPTF_TSR2_CRITICAL 70
#define DPTF_ENABLE_CHARGER
/* Charger performance states, board-specific values from charger and EC */

4
src/mainboard/google/cyan/variants/relm/gpio.c
View file

@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_END
};
/* South West Community */
static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_NC, /* 00 FST_SPI_D2 */
@ -131,7 +130,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_END
};
/* North Community */
static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 00 GPIO_DFX0 */
@ -201,7 +199,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_END
};
/* East Community */
static const struct soc_gpio_map gpe_gpio_map[] = {
Native_M1, /* 00 PMU_SLP_S3_B */
@ -231,7 +228,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = {
GPIO_END
};
static struct soc_gpio_config gpio_config = {
/* BSW */
.north = gpn_gpio_map,

2
src/mainboard/google/cyan/variants/relm/include/variant/acpi/dptf.asl
View file

@ -5,7 +5,6 @@
#define DPTF_TSR0_PASSIVE 49
#define DPTF_TSR0_CRITICAL 70
#define DPTF_TSR1_SENSOR_ID 1
#define DPTF_TSR1_SENSOR_NAME "TMP432_Charger"
#define DPTF_TSR1_PASSIVE 65
@ -16,7 +15,6 @@
#define DPTF_TSR2_PASSIVE 48
#define DPTF_TSR2_CRITICAL 70
#define DPTF_ENABLE_CHARGER
/* Charger performance states, board-specific values from charger and EC */

4
src/mainboard/google/cyan/variants/setzer/gpio.c
View file

@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_END
};
/* South West Community */
static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_NC, /* 00 FST_SPI_D2 */
@ -129,7 +128,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_END
};
/* North Community */
static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 00 GPIO_DFX0 */
@ -199,7 +197,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_END
};
/* East Community */
static const struct soc_gpio_map gpe_gpio_map[] = {
Native_M1, /* 00 PMU_SLP_S3_B */
@ -229,7 +226,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = {
GPIO_END
};
static struct soc_gpio_config gpio_config = {
/* BSW */
.north = gpn_gpio_map,

2
src/mainboard/google/cyan/variants/setzer/include/variant/acpi/dptf.asl
View file

@ -5,7 +5,6 @@
#define DPTF_TSR0_PASSIVE 58
#define DPTF_TSR0_CRITICAL 66
#define DPTF_TSR1_SENSOR_ID 1
#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
#define DPTF_TSR1_PASSIVE 57
@ -16,7 +15,6 @@
#define DPTF_TSR2_PASSIVE 59
#define DPTF_TSR2_CRITICAL 66
#define DPTF_ENABLE_CHARGER
/* Charger performance states, board-specific values from charger and EC */

4
src/mainboard/google/cyan/variants/terra/gpio.c
View file

@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_END
};
/* South West Community */
static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_NC, /* 00 FST_SPI_D2 */
@ -128,7 +127,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_END
};
/* North Community */
static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 00 GPIO_DFX0 */
@ -197,7 +195,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_END
};
/* East Community */
static const struct soc_gpio_map gpe_gpio_map[] = {
Native_M1, /* 00 PMU_SLP_S3_B */
@ -227,7 +224,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = {
GPIO_END
};
static struct soc_gpio_config gpio_config = {
/* BSW */
.north = gpn_gpio_map,

4
src/mainboard/google/cyan/variants/ultima/gpio.c
View file

@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_END
};
/* South West Community */
static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_NC, /* 00 FST_SPI_D2 */
@ -131,7 +130,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_END
};
/* North Community */
static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 00 GPIO_DFX0 */
@ -201,7 +199,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_END
};
/* East Community */
static const struct soc_gpio_map gpe_gpio_map[] = {
Native_M1, /* 00 PMU_SLP_S3_B */
@ -231,7 +228,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = {
GPIO_END
};
static struct soc_gpio_config gpio_config = {
/* BSW */
.north = gpn_gpio_map,

2
src/mainboard/google/cyan/variants/ultima/include/variant/acpi/dptf.asl
View file

@ -5,7 +5,6 @@
#define DPTF_TSR0_PASSIVE 60
#define DPTF_TSR0_CRITICAL 70
#define DPTF_TSR1_SENSOR_ID 1
#define DPTF_TSR1_SENSOR_NAME "TMP432_DDR"
#define DPTF_TSR1_PASSIVE 55
@ -16,7 +15,6 @@
#define DPTF_TSR2_PASSIVE 42
#define DPTF_TSR2_CRITICAL 70
#define DPTF_ENABLE_CHARGER
/* Charger performance states, board-specific values from charger and EC */

4
src/mainboard/google/cyan/variants/wizpig/gpio.c
View file

@ -64,7 +64,6 @@ static const struct soc_gpio_map gpse_gpio_map[] = {
GPIO_END
};
/* South West Community */
static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_NC, /* 00 FST_SPI_D2 */
@ -130,7 +129,6 @@ static const struct soc_gpio_map gpsw_gpio_map[] = {
GPIO_END
};
/* North Community */
static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_NC, /* 00 GPIO_DFX0 */
@ -200,7 +198,6 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPIO_END
};
/* East Community */
static const struct soc_gpio_map gpe_gpio_map[] = {
Native_M1, /* 00 PMU_SLP_S3_B */
@ -230,7 +227,6 @@ static const struct soc_gpio_map gpe_gpio_map[] = {
GPIO_END
};
static struct soc_gpio_config gpio_config = {
/* BSW */
.north = gpn_gpio_map,

2
src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/dptf.asl
View file

@ -5,7 +5,6 @@
#define DPTF_TSR0_PASSIVE 49
#define DPTF_TSR0_CRITICAL 75
#define DPTF_TSR1_SENSOR_ID 1
#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
#define DPTF_TSR1_PASSIVE 65
@ -16,7 +15,6 @@
#define DPTF_TSR2_PASSIVE 49
#define DPTF_TSR2_CRITICAL 75
#define DPTF_ENABLE_CHARGER
/* Charger performance states, board-specific values from charger and EC */

1
src/mainboard/google/dedede/dsdt.asl
View file

@ -37,7 +37,6 @@ DefinitionBlock(
#include <variant/acpi/camera.asl>
#endif
/* Include Low power idle table for a short term workaround to enable
S0ix. Once cr50 pulse width is fixed, this can be removed. */
#include <soc/intel/common/acpi/lpit.asl>

1
src/mainboard/google/dedede/romstage.c
View file

@ -32,7 +32,6 @@ bool mainboard_get_dram_part_num(const char **part_num, size_t *len)
return false;
}
*part_num = &part_num_store[0];
*len = strlen(part_num_store);
return true;

3
src/mainboard/google/dedede/variants/baseboard/gpio.c
View file

@ -238,7 +238,6 @@ static const struct pad_config gpio_table[] = {
/* E23 : CNV_RGI_RSP */
PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
/* F4 : CNV_RF_RST_L */
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
/* F7 : EMMC_CMD */
@ -341,7 +340,6 @@ static const struct pad_config gpio_table[] = {
/* R7 : I2S_SPK_AUDIO */
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF1),
/* S0 : RAM_STRAP_4 */
PAD_CFG_GPI(GPP_S0, NONE, DEEP),
/* S1 : RSVD_STRAP */
@ -359,7 +357,6 @@ static const struct pad_config gpio_table[] = {
/* S7 : DMIC0_DATA */
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
/* GPD0 : AP_BATLOW_L */
PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
/* GPD1 : GPP_GPD1/ACPRESENT */

1
src/mainboard/google/deltaur/mainboard.c
View file

@ -7,7 +7,6 @@
#include <vendorcode/google/chromeos/chromeos.h>
#include <variant/gpio.h>
static void mainboard_enable(struct device *dev)
{
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;

1
src/mainboard/google/gale/blsp.c
View file

@ -29,7 +29,6 @@
#endif
#if IPQ40XX_I2C1_PINGROUP_1
#define SCL_GPIO_I2C1 34

1
src/mainboard/google/gale/verstage.c
View file

@ -4,7 +4,6 @@
#include <gpio.h>
#include <soc/verstage.h>
#define TPM_RESET_GPIO 19
static void ipq_setup_tpm(void)

1
src/mainboard/google/glados/romstage.c
View file

@ -10,7 +10,6 @@
#include "spd/spd_util.h"
#include "spd/spd.h"
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;

1
src/mainboard/google/jecht/romstage.c
View file

@ -11,7 +11,6 @@
#include <mainboard/google/jecht/spd/spd.h>
#include "onboard.h"
void mainboard_pre_raminit(struct romstage_params *rp)
{
/* Fill out PEI DATA */

1
src/mainboard/google/kahlee/mainboard.c
View file

@ -160,7 +160,6 @@ static void kahlee_enable(struct device *dev)
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
}
static void mainboard_final(void *chip_info)
{
struct global_nvs *gnvs;

2
src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/routing.asl
View file

@ -13,7 +13,6 @@ Name (PR0, Package()
Package() { 0x0001FFFF, 2, INTE, 0 },
Package() { 0x0001FFFF, 3, INTF, 0 },
/* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */
Package() { 0x0002FFFF, 0, INTH, 0 },
Package() { 0x0002FFFF, 1, INTA, 0 },
@ -74,7 +73,6 @@ Name (APR0, Package()
Package() { 0x0011FFFF, 0, 0, 19 },
})
/* GPP 0 */
Name (PS4, Package()
{

1
src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h
View file

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __BASEBOARD_VARIANTS_H__
#define __BASEBOARD_VARIANTS_H__

1
src/mainboard/google/kahlee/variants/baseboard/mainboard.c
View file

@ -78,7 +78,6 @@ void board_bh720(struct device *dev)
write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000);
}
const char *smbios_mainboard_manufacturer(void)
{
static char oem_bin_data[11];

1
src/mainboard/google/kahlee/variants/nuwani/mainboard.c
View file

@ -90,7 +90,6 @@ void board_bh720(struct device *dev)
BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON);
}
const char *smbios_mainboard_manufacturer(void)
{
static char oem_bin_data[11];

1
src/mainboard/google/kahlee/variants/treeya/mainboard.c
View file

@ -90,7 +90,6 @@ void board_bh720(struct device *dev)
BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON);
}
const char *smbios_mainboard_manufacturer(void)
{
static char oem_bin_data[11];

1
src/mainboard/google/kukui/panel_anx7625.c
View file

@ -9,7 +9,6 @@
#include "panel.h"
static void power_on_anx7625(void)
{
/* Disable backlight before turning on bridge */

1
src/mainboard/google/kukui/panel_ps8640.c
View file

@ -9,7 +9,6 @@
#include "panel.h"
static void power_on_ps8640(void)
{
/* Disable backlight before turning on bridge */

1
src/mainboard/google/link/hda_verb.c
View file

@ -110,7 +110,6 @@ const u32 cim_verb_data[] = {
AZALIA_PIN_CFG(3, 0x07, 0x18560030),
};
const u32 pc_beep_verbs[] = {
0x00170500, /* power up codec */
0x00270500, /* power up DAC */

2
src/mainboard/google/link/mainboard.c
View file

@ -105,8 +105,6 @@ static int int15_handler(void)
}
#endif
static void mainboard_init(struct device *dev)
{
uint32_t board_version = 0;

1
src/mainboard/google/octopus/variants/bobba/variant.c
View file

@ -47,7 +47,6 @@ void variant_smi_sleep(u8 slp_typ)
}
}
void variant_update_devtree(struct device *dev)
{
struct soc_intel_apollolake_config *cfg = NULL;

1
src/mainboard/google/parrot/acpi/superio.asl
View file

@ -3,7 +3,6 @@
/* mainboard configuration */
#include "../ec.h"
#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
/* ACPI code for EC SuperIO functions */

1
src/mainboard/google/parrot/acpi_tables.c
View file

@ -22,7 +22,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
#if CONFIG(CHROMEOS)
gnvs->chromeos.vbt2 = parrot_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;

2
src/mainboard/google/parrot/ec.c
View file

@ -7,7 +7,6 @@
#include <ec/compal/ene932/ec.h>
#include "ec.h"
void parrot_ec_init(void)
{
printk(BIOS_DEBUG, "Parrot EC Init\n");
@ -53,7 +52,6 @@ void parrot_ec_init(void)
ec_kbc_write_ib(0xA2);
}
/* Parrot Hardware Revision */
u8 parrot_rev(void)
{

1
src/mainboard/google/parrot/hda_verb.c
View file

@ -23,7 +23,6 @@ const u32 cim_verb_data[] = {
0x10250742, // Subsystem ID
0x0000000E, // Number of jacks (NID entries)
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10250742 */
AZALIA_SUBVENDOR(0, 0x10250742),

1
src/mainboard/google/parrot/mainboard.c
View file

@ -18,7 +18,6 @@ void mainboard_suspend_resume(void)
apm_control(APM_CNT_ACPI_ENABLE);
}
static void mainboard_init(struct device *dev)
{
/* Initialize the Embedded Controller */

3
src/mainboard/google/parrot/smihandler.c
View file

@ -54,13 +54,10 @@ void mainboard_smi_sleep(u8 slp_typ)
printk(BIOS_DEBUG, "mainboard_smi_sleep: %x\n", slp_typ);
/* Disable SCI and SMI events */
/* Clear pending events that may trigger immediate wake */
/* Enable wake events */
/* Tell the EC to Disable USB power */
if (gnvs->s3u0 == 0 && gnvs->s3u1 == 0) {
ec_kbc_write_cmd(0x45);

1
src/mainboard/google/peach_pit/mainboard.c
View file

@ -231,7 +231,6 @@ static void parade_dp_bridge_setup(void)
udelay(10);
gpio_set_value(dp_rst_l, 1);
gpio_set_pull(dp_hpd, GPIO_PULL_NONE);
gpio_cfg_pin(dp_hpd, GPIO_INPUT);

1
src/mainboard/google/peach_pit/romstage.c
View file

@ -176,7 +176,6 @@ static void simple_spi_test(void)
return;
}
for (i = 0; i < amt; i += 4){
if (rdev_readat(boot_dev, &in, i, 4) < 4) {
printk(BIOS_SPEW, "simple_spi_test fails at %d\n", i);

1
src/mainboard/google/poppy/chromeos.c
View file

@ -9,7 +9,6 @@
#include <variant/gpio.h>
void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {

1
src/mainboard/google/poppy/variants/atlas/gpio.c
View file

@ -388,7 +388,6 @@ static const struct pad_config ish_enabled_gpio_table[] = {
PAD_CFG_NF_1V8(GPP_D14, NONE, DEEP, NF1),
};
static const struct pad_config ish_disabled_gpio_table[] = {
/* A19 : GPP_A19 ==> TRACKPAD_INT_L
* trackpad interrupt to PCH

1
src/mainboard/google/poppy/variants/atlas/include/variant/acpi/cam0.asl
View file

@ -65,7 +65,6 @@ Scope (\_SB.PCI0.I2C3)
Name (_PR0, Package (0x01) { FCPR })
Name (_PR3, Package (0x01) { FCPR })
/* Port0 of CAM0 is connected to port0 of CIO2 device */
Name (_DSD, Package () {
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),

1
src/mainboard/google/rambi/variants/clapper/gpio.c
View file

@ -197,7 +197,6 @@ static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
[I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
};
static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
[CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
};

1
src/mainboard/google/reef/variants/pyro/memory.c
View file

@ -5,7 +5,6 @@
#include <soc/meminit.h>
#include <variant/gpio.h>
static const struct lpddr4_sku skus[] = {
/*
* K4F6E304HB-MGCJ - both logical channels While the parts

1
src/mainboard/google/reef/variants/sand/include/variant/ec.h
View file

@ -60,7 +60,6 @@
#define EC_ENABLE_LID_SWITCH
#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */

1
src/mainboard/google/slippy/acpi_tables.c
View file

@ -23,7 +23,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
/* TPM Present */
gnvs->tpmp = 1;
#if CONFIG(CHROMEOS)
gnvs->chromeos.vbt2 = google_ec_running_ro() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;

2
src/mainboard/google/slippy/mainboard.c
View file

@ -16,8 +16,6 @@ void mainboard_suspend_resume(void)
apm_control(APM_CNT_FINALIZE);
}
static void mainboard_init(struct device *dev)
{
mainboard_ec_init();

1
src/mainboard/google/stout/acpi_tables.c
View file

@ -23,7 +23,6 @@ void acpi_create_gnvs(struct global_nvs *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
#if CONFIG(CHROMEOS)
gnvs->chromeos.vbt2 = get_recovery_mode_switch() ?
ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;

3
src/mainboard/google/stout/ec.c
View file

@ -55,14 +55,12 @@ void stout_ec_finalize_smm(void)
critical_shutdown = 1;
}
/* Thermal Device Error : Peripheral Status 3 (0x35) bit 8 */
if (ec_reg & 0x80) {
printk(BIOS_ERR, " EC Thermal Device Error\n");
critical_shutdown = 1;
}
/* Critical Battery Error */
ec_reg = ec_read(EC_MBAT_STATUS);
@ -75,7 +73,6 @@ void stout_ec_finalize_smm(void)
printk(BIOS_ERR, " EC Read Battery Error\n");
}
if (critical_shutdown) {
printk(BIOS_ERR, "EC critical_shutdown");

2
src/mainboard/google/stout/mainboard.c
View file

@ -17,8 +17,6 @@ void mainboard_suspend_resume(void)
ec_write_cmd(EC_CMD_NOTIFY_ACPI_ENTER);
}
static void mainboard_init(struct device *dev)
{
struct device *ethernet_dev = NULL;

1
src/mainboard/google/veyron_rialto/chromeos.c
View file

@ -11,7 +11,6 @@
#define GPIO_RECOVERY_SERVO GPIO(0, B, 1)
#define GPIO_RECOVERY_PUSHKEY GPIO(7, B, 1)
void setup_chromeos_gpios(void)
{
gpio_input(GPIO_WP);

1
src/mainboard/google/volteer/romstage.c
View file

@ -11,7 +11,6 @@
#include <soc/romstage.h>
#include <variant/gpio.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;

1
src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
View file

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __BASEBOARD_VARIANTS_H__
#define __BASEBOARD_VARIANTS_H__

1
src/mainboard/google/zork/variants/baseboard/ramstage_common.c
View file

@ -127,7 +127,6 @@ void variant_audio_update(void)
update_hp_int_odl();
}
/*
* Removes reset_gpio from usb device in device tree.
*