diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
index f0ee6afedd..77ae4838cc 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -1439,6 +1439,10 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
 						/* Back up the Nibble 0 delays for later use */
 						memcpy(nibble0_current_total_delay, current_total_delay, sizeof(current_total_delay));
 					}
+
+					/* Exit nibble training if current DIMM is not x4 */
+					if ((pDCTstat->Dimmx4Present & (1 << (dimm + Channel))) == 0)
+						break;
 				}
 
 				if (_2Ranks) {
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
index c6ec9052fc..ffc6fb2df0 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
@@ -184,6 +184,10 @@ uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT
 		}
 
 		pDCTData->WLCriticalGrossDelayPrevPass = 0x0;
+
+		/* Exit nibble training if current DIMM is not x4 */
+		if ((pDCTstat->Dimmx4Present & (1 << (dimm + dct))) == 0)
+			break;
 	}
 
 	return 0;