mb/google/brya/var/vell: update overridetree
Init basic override devicetree based on initial schematics BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Ibaa910eb1c5584197907963781258035c668298e Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Kevin Chiu
Felix Held
parent
1ca8b6e3c3
commit
2649f5a518
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@ -127,6 +127,8 @@ config BOARD_GOOGLE_ANAHERA4ES
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config BOARD_GOOGLE_VELL
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bool "-> Vell"
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select BOARD_GOOGLE_BASEBOARD_BRYA
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select DRIVERS_GFX_GENERIC
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select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
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config BOARD_GOOGLE_TANIKS
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bool "-> Taniks"
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@ -1,6 +1,339 @@
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chip soc/intel/alderlake
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device domain 0 on
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end
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fw_config
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field DB_SD 0 1
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option SD_ABSENT 0
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option SD_GL9750 1
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end
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field KB_BL 2 2
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option KB_BL_ABSENT 0
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option KB_BL_PRESENT 1
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end
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field AUDIO 3 5
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option AUDIO_UNKNOWN 0
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option MAX98360_ALC5682I_I2S 1
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option MAX98360_ALC5682IVS_I2S 2
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end
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field DB_LTE 6 7
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option LTE_ABSENT 0
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option LTE_USB 1
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end
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field EPS 10 10
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option PRIVACY_SCREEN_ABSENT 0
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option PRIVACY_SCREEN 1
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end
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end
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chip soc/intel/alderlake
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# This disables autonomous GPIO power management, otherwise
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# old cr50 FW only supports short pulses; need to clarify
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# the minimum PCH IRQ pulse width with Intel, b/180111628
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register "gpio_override_pm" = "1"
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register "gpio_pm[COMM_0]" = "0"
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register "gpio_pm[COMM_1]" = "0"
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register "gpio_pm[COMM_2]" = "0"
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register "gpio_pm[COMM_3]" = "0"
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register "gpio_pm[COMM_4]" = "0"
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register "gpio_pm[COMM_5]" = "0"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| GSPI1 | Fingerprint MCU |
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#| I2C0 | Audio |
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#| I2C1 | Touchscreen |
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#| I2C2 | |
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#| I2C3 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| I2C5 | Trackpad |
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#+-------------------+---------------------------+
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register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Smart Card
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
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device domain 0 on
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device ref igpu on
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chip drivers/gfx/generic
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register "device_count" = "1"
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register "device[0].name" = ""LCD""
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# Use Chrome OS privacy screen _HID
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register "device[0].hid" = ""GOOG0010""
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# Internal panel on the first port of the graphics chip
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register "device[0].addr" = "0x80010400"
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register "device[0].privacy.enabled" = "1"
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register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H21)"
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device generic 0 on
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probe EPS PRIVACY_SCREEN
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end
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end
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end # Integrated Graphics Device
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device ref dtt on
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chip drivers/intel/dptf
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## sensor information
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register "options.tsr[0].desc" = ""DRAM""
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register "options.tsr[1].desc" = ""Soc""
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register "options.tsr[2].desc" = ""Charger""
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register "options.tsr[3].desc" = ""Regulator""
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# TODO: below values are initial reference values only
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## Passive Policy
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
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[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000),
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[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000),
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[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000),
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}"
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## Critical Policy
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
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[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
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[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
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}"
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 3000,
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.max_power = 15000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 200,
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},
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.pl2 = {
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.min_power = 55000,
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.max_power = 55000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 1000,
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}
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}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf" = "{
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[0] = { 255, 1700 },
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[1] = { 24, 1500 },
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[2] = { 16, 1000 },
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[3] = { 8, 500 }
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}"
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device generic 0 on end
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end
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end
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device ref pcie4_0 on
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# Enable CPU PCIE RP 1 using CLK 0
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register "cpu_pcie_rp[CPU_RP(1)]" = "{
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.clk_req = 1,
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.clk_src = 3,
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}"
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end
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device ref cnvi_wifi on
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chip drivers/wifi/generic
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register "wake" = "GPE0_PME_B0"
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device generic 0 on end
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end
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end
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device ref pcie_rp8 off end
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device ref pcie_rp9 off end
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device ref tcss_dma0 on
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chip drivers/intel/usb4/retimer
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register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
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use tcss_usb3_port1 as dfp[0].typec_port
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device generic 0 on end
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end
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end
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device ref tcss_dma1 on
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chip drivers/intel/usb4/retimer
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register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
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use tcss_usb3_port3 as dfp[0].typec_port
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device generic 0 on end
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end
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end
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device ref i2c0 on
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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register "name" = ""RT58""
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register "desc" = ""Headset Codec""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
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# Set the jd_src to RT5668_JD1 for jack detection
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register "property_count" = "1"
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on
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probe AUDIO MAX98360_ALC5682I_I2S
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end
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end
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chip drivers/i2c/generic
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register "hid" = ""RTL5682""
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register "name" = ""RT58""
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register "desc" = ""Headset Codec""
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register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
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# Set the jd_src to RT5668_JD1 for jack detection
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register "property_count" = "1"
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register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
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register "property_list[0].name" = ""realtek,jd-src""
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register "property_list[0].integer" = "1"
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device i2c 1a on
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probe AUDIO MAX98360_ALC5682IVS_I2S
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end
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end
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end #I2C0
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device ref i2c1 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0001""
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register "desc" = ""ELAN Touchscreen""
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register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
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register "probed" = "1"
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register "reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
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register "reset_delay_ms" = "100"
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register "reset_off_delay_ms" = "5"
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register "enable_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
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register "enable_delay_ms" = "10"
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register "enable_off_delay_ms" = "1"
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register "stop_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
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register "has_power_resource" = "1"
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device i2c 10 on end
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end
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chip drivers/i2c/hid
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register "generic.hid" = ""GTCH7503""
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register "generic.desc" = ""G2TOUCH Touchscreen""
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register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
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register "generic.probed" = "1"
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register "generic.reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
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register "generic.reset_delay_ms" = "50"
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register "generic.enable_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
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register "generic.enable_delay_ms" = "1"
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register "generic.has_power_resource" = "1"
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register "hid_desc_reg_offset" = "0x01"
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device i2c 40 on end
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end
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end
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device ref i2c5 on
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
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register "wake" = "GPE0_DW2_14"
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register "probed" = "1"
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device i2c 15 on end
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end
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end
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device ref gspi1 on
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chip drivers/spi/acpi
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register "name" = ""CRFP""
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register "hid" = "ACPI_DT_NAMESPACE_HID"
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register "uid" = "1"
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register "compat_string" = ""google,cros-ec-spi""
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register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
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register "wake" = "GPE0_DW2_15"
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device spi 0 on end
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end # FPMCU
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end
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device ref pch_espi on
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chip ec/google/chromeec
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use conn0 as mux_conn[0]
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use conn1 as mux_conn[1]
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device pnp 0c09.0 on end
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end
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end
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device ref pmc hidden
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chip drivers/intel/pmc_mux
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device generic 0 on
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chip drivers/intel/pmc_mux/conn
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register "usb2_port_number" = "1"
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register "usb3_port_number" = "1"
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device generic 0 alias conn0 on end
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end
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chip drivers/intel/pmc_mux/conn
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register "usb2_port_number" = "3"
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register "usb3_port_number" = "3"
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device generic 1 alias conn1 on end
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end
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end
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end
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end
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device ref tcss_xhci on
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chip drivers/usb/acpi
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(1, 1)"
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device ref tcss_usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C2 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(3, 1)"
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device ref tcss_usb3_port3 on end
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end
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end
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end
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end
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device ref xhci on
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C0 (MLB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(1, 1)"
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device ref usb2_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port (MLB)""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(4, 2)"
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device ref usb2_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C2 (DB)""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "group" = "ACPI_PLD_GROUP(3, 1)"
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device ref usb2_port3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 WWAN""
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register "type" = "UPC_TYPE_INTERNAL"
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device ref usb2_port4 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Camera""
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register "type" = "UPC_TYPE_INTERNAL"
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device ref usb2_port6 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port (DB)""
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register "type" = "UPC_TYPE_A"
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register "group" = "ACPI_PLD_GROUP(4, 1)"
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device ref usb2_port9 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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register "reset_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
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device ref usb2_port10 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port (DB)""
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(4, 1)"
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device ref usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port (MLB)""
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register "type" = "UPC_TYPE_USB3_A"
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register "group" = "ACPI_PLD_GROUP(4, 2)"
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device ref usb3_port3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 WWAN""
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register "type" = "UPC_TYPE_INTERNAL"
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device ref usb3_port4 on end
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end
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end
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end
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end
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end
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end
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