mb/siemens/mc_ehl: Add a new variant mc_ehl2
Add a new variant of the mc_ehl board called mc_ehl2. This patch just copies the files and renames things where needed. Following patches will adapt the needed features for this new variant. Change-Id: I3ec3c091017fd66fe6a09216203cdc7c9e833846 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This commit is contained in:
Werner Zeh
Felix Held
parent
0bebcdb165
commit
264ace99e8
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@ -22,9 +22,11 @@ config MAINBOARD_DIR
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config VARIANT_DIR
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default "mc_ehl1" if BOARD_SIEMENS_MC_EHL1
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default "mc_ehl2" if BOARD_SIEMENS_MC_EHL2
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config MAINBOARD_PART_NUMBER
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default "MC EHL1" if BOARD_SIEMENS_MC_EHL1
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default "MC EHL2" if BOARD_SIEMENS_MC_EHL2
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config DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
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@ -3,3 +3,7 @@ comment "MC EHLx"
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config BOARD_SIEMENS_MC_EHL1
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bool "-> MC EHL1"
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select BOARD_SIEMENS_BASEBOARD_MC_EHL
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config BOARD_SIEMENS_MC_EHL2
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bool "-> MC EHL2"
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select BOARD_SIEMENS_BASEBOARD_MC_EHL
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@ -0,0 +1,11 @@
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if BOARD_SIEMENS_MC_EHL2
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select DRIVER_INTEL_I210
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select INTEL_LPSS_UART_FOR_CONSOLE
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config FMDFILE
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_ehl.fmd"
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endif # BOARD_SIEMENS_MC_EHL2
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@ -0,0 +1,9 @@
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## SPDX-License-Identifier: GPL-2.0-only
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bootblock-y += gpio.c
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romstage-y += memory.c
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ramstage-y += gpio.c
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SPD_SOURCES = mc_ehl2 # 0b000
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LIB_SPD_DEPS := $(foreach f, $(SPD_SOURCES), \
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src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex)
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@ -0,0 +1,262 @@
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chip soc/intel/elkhartlake
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "pmc_gpe0_dw0" = "GPP_B"
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register "pmc_gpe0_dw1" = "GPP_F"
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register "pmc_gpe0_dw2" = "GPP_E"
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# Enable heci1 communication
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register "HeciEnabled" = "1"
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# FSP configuration
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register "SaGv" = "SaGv_Disabled"
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register "SmbusEnable" = "1"
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register "Heci2Enable" = "1"
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# Enable IBECC for the complete memory
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register "ibecc" = "{
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.enable = 1,
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.mode = IBECC_ALL
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}"
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# USB related UPDs
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register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A port 1
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register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # USB3/2 Type A Port 2
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Onboard USB
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register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Port is unused
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register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Port is unused
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register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Port is unused
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register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Port is unused
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register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Port is unused
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register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Port is unused
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register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Port is unused
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port2
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register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Port is not used
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register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Port is not used
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# Skip the CPU repalcement check
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register "SkipCpuReplacementCheck" = "1"
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# PCIe root ports related UPDs
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register "PcieRpEnable[0]" = "1"
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register "PcieRpEnable[1]" = "1"
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register "PcieRpEnable[2]" = "1"
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register "PcieRpEnable[3]" = "1"
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register "PcieRpEnable[4]" = "1"
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register "PcieRpEnable[5]" = "1"
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register "PcieRpEnable[6]" = "1"
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register "PcieClkSrcUsage[0]" = "0x00"
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register "PcieClkSrcUsage[1]" = "0x01"
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register "PcieClkSrcUsage[2]" = "0x02"
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register "PcieClkSrcUsage[3]" = "0xFF"
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register "PcieClkSrcUsage[4]" = "0xFF"
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register "PcieClkSrcUsage[5]" = "0xFF"
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register "PcieClkSrcClkReq[0]" = "0xFF"
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register "PcieClkSrcClkReq[1]" = "0xFF"
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register "PcieClkSrcClkReq[2]" = "0xFF"
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register "PcieClkSrcClkReq[3]" = "0xFF"
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register "PcieClkSrcClkReq[4]" = "0xFF"
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register "PcieClkSrcClkReq[5]" = "0xFF"
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# Disable all L1 substates for PCIe root ports
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register "PcieRpL1Substates[0]" = "L1_SS_DISABLED"
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register "PcieRpL1Substates[1]" = "L1_SS_DISABLED"
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register "PcieRpL1Substates[2]" = "L1_SS_DISABLED"
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register "PcieRpL1Substates[3]" = "L1_SS_DISABLED"
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register "PcieRpL1Substates[4]" = "L1_SS_DISABLED"
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register "PcieRpL1Substates[5]" = "L1_SS_DISABLED"
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# Disable LTR for all PCIe root ports
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register "PcieRpLtrDisable[0]" = "true"
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register "PcieRpLtrDisable[1]" = "true"
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register "PcieRpLtrDisable[2]" = "true"
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register "PcieRpLtrDisable[3]" = "true"
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register "PcieRpLtrDisable[4]" = "true"
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register "PcieRpLtrDisable[5]" = "true"
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# Storage (SATA/SDCARD/EMMC) related UPDs
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register "SataSalpSupport" = "0"
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register "SataPortsEnable[0]" = "1"
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register "SataPortsEnable[1]" = "1"
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register "SataPortsDevSlp[0]" = "0"
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register "SataPortsDevSlp[1]" = "0"
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register "ScsEmmcHs400Enabled" = "1"
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register "ScsEmmcDdr50Enabled" = "1"
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register "SdCardPowerEnableActiveHigh" = "1"
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# LPSS Serial IO (I2C/UART/GSPI) related UPDs
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register "SerialIoI2cMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C4] = PchSerialIoPci,
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[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C6] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
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}"
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register "SerialIoI2cPadsTermination" = "{
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[PchSerialIoIndexI2C0] = 1,
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[PchSerialIoIndexI2C1] = 1,
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[PchSerialIoIndexI2C2] = 1,
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[PchSerialIoIndexI2C3] = 1,
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[PchSerialIoIndexI2C4] = 1,
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[PchSerialIoIndexI2C5] = 1,
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[PchSerialIoIndexI2C6] = 1,
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[PchSerialIoIndexI2C7] = 1,
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}"
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register "SerialIoUartMode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoDisabled,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
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}"
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register "SerialIoUartDmaEnable" = "{
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[PchSerialIoIndexUART0] = 1,
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[PchSerialIoIndexUART1] = 1,
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[PchSerialIoIndexUART2] = 1,
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}"
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# TSN GBE related UPDs
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register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps"
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register "PchTsnGbeSgmiiEnable" = "1"
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 off end # SA Thermal device
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device pci 08.0 off end # GNA
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device pci 09.0 off end # CPU Intel Trace Hub
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device pci 10.0 off end # I2C6
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device pci 10.1 off end # I2C7
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device pci 10.5 on end # Integrated Error Handler
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device pci 11.0 off end # Intel PSE UART0
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device pci 11.1 off end # Intel PSE UART1
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device pci 11.2 off end # Intel PSE UART2
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device pci 11.3 off end # Intel PSE UART3
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device pci 11.4 off end # Intel PSE UART4
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device pci 11.5 off end # Intel PSE UART5
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device pci 11.6 off end # Intel PSE IS20
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device pci 11.7 off end # Intel PSE IS21
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device pci 12.0 off end # GSPI2
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device pci 12.3 on end # Management Engine UMA Access
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device pci 12.4 on end # Management Engine PTT DMA Controller
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device pci 12.5 off end # UFS0
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device pci 12.7 off end # UFS1
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device pci 13.0 off end # Intel PSE GSPI0
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device pci 13.1 off end # Intel PSE GSPI1
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device pci 13.2 off end # Intel PSE GSPI2
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device pci 13.3 off end # Intel PSE GSPI3
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device pci 13.4 off end # Intel PSE GPIO0
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device pci 13.5 off end # Intel PSE GPIO1
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device pci 14.0 on end # USB3.1 xHCI
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device pci 14.1 off end # USB3.1 xDCI (OTG)
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device pci 15.0 off end # I2C0
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device pci 15.1 on end # I2C1
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device pci 15.2 off end # I2C2
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device pci 15.3 off end # I2C3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 on end # Management Engine Interface 2
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device pci 16.4 on end # Management Engine Interface 3
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device pci 16.5 on end # Management Engine Interface 4
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device pci 17.0 on end # SATA
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device pci 18.0 off end # Intel PSE I2C7
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device pci 18.1 off end # Intel PSE CAN0
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device pci 18.2 off end # Intel PSE CAN1
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device pci 18.3 off end # Intel PSE QEP0
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device pci 18.4 off end # Intel PSE QEP1
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device pci 18.5 off end # Intel PSE QEP2
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device pci 18.6 off end # Intel PSE QEP3
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device pci 19.0 on end # I2C4
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device pci 19.1 off end # I2C5
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device pci 19.2 on end # UART2
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device pci 1a.0 on end # eMMC
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device pci 1a.1 off end # SD
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device pci 1a.3 off end # Intel Safety Island
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device pci 1b.0 off end # Intel PSE I2C0
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device pci 1b.1 off end # Intel PSE I2C1
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device pci 1b.2 off end # Intel PSE I2C2
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device pci 1b.3 off end # Intel PSE I2C3
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device pci 1b.4 off end # Intel PSE I2C4
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device pci 1b.5 off end # Intel PSE I2C5
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device pci 1b.6 off end # Intel PSE I2C6
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device pci 1c.0 on end # RP1 (pcie0 single VC)
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device pci 1c.1 on end # RP2 (pcie0 single VC)
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device pci 1c.2 on end # RP3 (pcie0 single VC)
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device pci 1c.3 on end # RP4 (pcie0 single VC)
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device pci 1c.4 on end # RP5 (pcie1 multi VC)
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device pci 1c.5 on end # RP6 (pcie2 multi VC)
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device pci 1c.6 on end # RP7 (pcie3 multi VC)
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device pci 1d.0 off end # Intel PSE IPC (local host to PSE)
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device pci 1d.1 on end # Intel PSE Time-Sensitive Networking GbE 0
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device pci 1d.2 on end # Intel PSE Time-Sensitive Networking GbE 1
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device pci 1d.3 off end # Intel PSE DMA0
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device pci 1d.4 off end # Intel PSE DMA1
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device pci 1d.5 off end # Intel PSE DMA2
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device pci 1d.6 off end # Intel PSE PWM
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device pci 1d.7 off end # Intel PSE ADC
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device pci 1e.0 on end # UART0
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device pci 1e.1 on end # UART1
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device pci 1e.2 off end # GSPI0
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device pci 1e.3 off end # GSPI1
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device pci 1e.4 on end # PCH Time-Sensitive Networking GbE
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device pci 1e.6 on end # HPET
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device pci 1e.7 on end # IOAPIC
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device pci 1f.0 on # eSPI Interface
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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end
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device pci 1f.1 on end # P2SB
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device pci 1f.2 hidden end # Power Management Controller
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device pci 1f.3 off end # Intel cAVS/HDA
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device pci 1f.4 on # SMBus
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# Enable external RTC chip
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chip drivers/i2c/rx6110sa
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register "bus_speed" = "I2C_SPEED_STANDARD"
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register "pmon_sampling" = "PMON_SAMPL_256_MS"
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register "bks_on" = "0"
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register "bks_off" = "1"
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register "iocut_en" = "1"
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register "set_user_date" = "1"
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register "user_year" = "04"
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register "user_month" = "07"
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register "user_day" = "01"
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register "user_weekday" = "4"
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device i2c 0x32 on end # RTC RX6110 SA
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end
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end
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device pci 1f.5 on end # PCH SPI (flash & TPM)
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device pci 1f.7 off end # PCH Intel Trace Hub
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end
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end
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@ -0,0 +1,178 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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/* Pad configuration in ramstage*/
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static const struct pad_config gpio_table[] = {
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/* Community 0 - GpioGroup GPP_B */
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PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* PMC_VRALERT_N */
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PAD_CFG_NF(GPP_B3, NONE, PLTRST, NF4), /* ESPI_ALERT0_N */
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PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF4), /* ESPI_ALERT1_N */
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PAD_NC(GPP_B9, NONE), /* Not connected */
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PAD_NC(GPP_B10, NONE), /* Not connected */
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PAD_CFG_NF(GPP_B11, NONE, PLTRST, NF1), /* PMC_ALERT_N */
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PAD_NC(GPP_B14, NONE), /* Not connected */
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PAD_CFG_NF(GPP_B15, NONE, PLTRST, NF5), /* ESPI_CS1_N */
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PAD_NC(GPP_B18, NONE), /* Not connected */
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PAD_NC(GPP_B19, NONE), /* Not connected */
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PAD_NC(GPP_B20, NONE), /* Not connected */
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PAD_NC(GPP_B21, NONE), /* Not connected */
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PAD_NC(GPP_B22, NONE), /* Not connected */
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PAD_NC(GPP_B23, NONE), /* Not connected */
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/* Community 0 - GpioGroup GPP_T */
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PAD_CFG_NF(GPP_T4, UP_20K, DEEP, NF1), /* PSE_GBE0_INT */
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PAD_CFG_NF(GPP_T5, DN_20K, DEEP, NF1), /* PSE_GBE0_RST_N */
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PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */
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PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */
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PAD_CFG_NF(GPP_T12, NONE, DEEP, NF2), /* SIO_UART0_RXD */
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PAD_CFG_NF(GPP_T13, NONE, DEEP, NF2), /* SIO_UART0_TXD */
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/* Community 0 - GpioGroup GPP_G */
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PAD_NC(GPP_G8, NONE), /* Not connected */
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PAD_NC(GPP_G9, NONE), /* Not connected */
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PAD_NC(GPP_G12, NONE), /* Not connected */
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PAD_CFG_NF(GPP_G15, NONE, DEEP, NF1), /* ESPI_IO_0 */
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PAD_CFG_NF(GPP_G16, NONE, DEEP, NF1), /* ESPI_IO_1 */
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PAD_CFG_NF(GPP_G17, NONE, DEEP, NF1), /* ESPI_IO_2 */
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PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), /* ESPI_IO_3 */
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PAD_CFG_GPI(GPP_G19, UP_20K, PLTRST), /* TPM_IRQ_N */
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PAD_CFG_NF(GPP_G20, NONE, DEEP, NF1), /* ESPI_CSO_N */
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PAD_CFG_NF(GPP_G21, NONE, DEEP, NF1), /* ESPI_CLK */
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PAD_CFG_NF(GPP_G22, NONE, DEEP, NF1), /* ESPI_RST0_N */
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/* Community 1 - GpioGroup GPP_V */
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PAD_CFG_NF(GPP_V0, UP_20K, DEEP, NF1), /* EMMC_CMD */
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PAD_CFG_NF(GPP_V1, UP_20K, DEEP, NF1), /* EMMC_DATA0 */
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PAD_CFG_NF(GPP_V2, UP_20K, DEEP, NF1), /* EMMC_DATA1 */
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PAD_CFG_NF(GPP_V3, UP_20K, DEEP, NF1), /* EMMC_DATA2 */
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PAD_CFG_NF(GPP_V4, UP_20K, DEEP, NF1), /* EMMC_DATA3 */
|
||||
PAD_CFG_NF(GPP_V5, UP_20K, DEEP, NF1), /* EMMC_DATA4 */
|
||||
PAD_CFG_NF(GPP_V6, UP_20K, DEEP, NF1), /* EMMC_DATA5 */
|
||||
PAD_CFG_NF(GPP_V7, UP_20K, DEEP, NF1), /* EMMC_DATA6 */
|
||||
PAD_CFG_NF(GPP_V8, UP_20K, DEEP, NF1), /* EMMC_DATA7 */
|
||||
PAD_CFG_NF(GPP_V9, DN_20K, DEEP, NF1), /* EMMC_RCLK */
|
||||
PAD_CFG_NF(GPP_V10, DN_20K, DEEP, NF1), /* EMMC_CLK */
|
||||
PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), /* EMMC_RESET_N */
|
||||
|
||||
/* Community 1 - GpioGroup GPP_H */
|
||||
PAD_CFG_NF(GPP_H0, DN_20K, DEEP, NF1), /* PSE_GBE1_INT */
|
||||
PAD_CFG_NF(GPP_H1, DN_20K, DEEP, NF1), /* PSE_GBE1_RST_N */
|
||||
PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), /* PSE_GBE1_AUXTS */
|
||||
PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), /* PSE_GBE1_PPS */
|
||||
PAD_CFG_NF(GPP_H8, UP_20K, DEEP, NF1), /* SIO_I2C4_SDA */
|
||||
PAD_CFG_NF(GPP_H9, UP_20K, DEEP, NF1), /* SIO_I2C4_SCL */
|
||||
|
||||
/* Community 1 - GpioGroup GPP_D */
|
||||
PAD_CFG_GPO(GPP_D16, 0, DEEP), /* EMMC_PWR_EN_N */
|
||||
|
||||
/* Community 1 - GpioGroup GPP_U */
|
||||
PAD_CFG_NF(GPP_U0, DN_20K, DEEP, NF1), /* GBE_INT */
|
||||
PAD_CFG_NF(GPP_U1, DN_20K, DEEP, NF1), /* GBE_RST_N */
|
||||
PAD_CFG_NF(GPP_U2, NONE, DEEP, NF1), /* GBE_PPS */
|
||||
PAD_CFG_NF(GPP_U3, NONE, DEEP, NF1), /* GBE_AUXTS */
|
||||
PAD_NC(GPP_U12, NONE), /* Not connected */
|
||||
PAD_NC(GPP_U13, NONE), /* Not connected */
|
||||
PAD_NC(GPP_U16, NONE), /* Not connected */
|
||||
PAD_NC(GPP_U17, NONE), /* Not connected */
|
||||
PAD_NC(GPP_U18, NONE), /* Not connected */
|
||||
PAD_CFG_GPO(GPP_U19, 1, DEEP), /* UPD_REQ_N */
|
||||
|
||||
/* Community 2 - GpioGroup DSW */
|
||||
PAD_CFG_NF(GPD4, NONE, PLTRST, NF1), /* SLP_S3 */
|
||||
PAD_CFG_NF(GPD5, NONE, PLTRST, NF1), /* SLP_S4 */
|
||||
PAD_NC(GPD7, NONE), /* Not connected */
|
||||
PAD_CFG_NF(GPD10, NONE, PLTRST, NF1), /* SLP_S5 */
|
||||
|
||||
/* Community 3 - GpioGroup GPP_S */
|
||||
PAD_NC(GPP_S0, NONE), /* Not connected */
|
||||
PAD_NC(GPP_S1, NONE), /* Not connected */
|
||||
|
||||
/* Community 3 - GpioGroup GPP_A */
|
||||
PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD3 */
|
||||
PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD2 */
|
||||
PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD1 */
|
||||
PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXD0 */
|
||||
PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCLK */
|
||||
PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_TXCTL */
|
||||
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCLK */
|
||||
PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD3 */
|
||||
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD2 */
|
||||
PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD1 */
|
||||
PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXD0 */
|
||||
PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* PSE_GBE0_RGMII_RXCTL */
|
||||
|
||||
/* Community 4 - GpioGroup GPP_C */
|
||||
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* PSE_GBE0_MDC */
|
||||
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* PSE_GBE0_MDIO */
|
||||
PAD_NC(GPP_C5, NONE), /* Not connected */
|
||||
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* PSE_GBE0_AUXTS */
|
||||
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* PSE_GBE0_PPS */
|
||||
PAD_NC(GPP_C8, NONE), /* Not connected */
|
||||
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF4), /* SIO_UART1_RXD */
|
||||
PAD_CFG_NF(GPP_C13, NONE, DEEP, NF4), /* SIO_UART1_TXD */
|
||||
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* GBE_MDIO */
|
||||
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* GBE_MDC */
|
||||
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF4), /* SIO_I2C1_SDA */
|
||||
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF4), /* SIO_I2C1_SCL */
|
||||
|
||||
/* Community 4 - GpioGroup GPP_F */
|
||||
PAD_NC(GPP_F0, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F1, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F2, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F3, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F4, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F5, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F7, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F8, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F10, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F11, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F12, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F13, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F14, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F15, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F16, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F17, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F20, NONE), /* Not connected */
|
||||
PAD_NC(GPP_F21, NONE), /* Not connected */
|
||||
|
||||
/* Community 4 - GpioGroup GPP_E */
|
||||
PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), /* SATA_LED_N */
|
||||
PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), /* DDI1_HPD */
|
||||
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DDI1_DDC_SDA */
|
||||
PAD_NC(GPP_E6, NONE), /* Not connected */
|
||||
PAD_CFG_NF(GPP_E7, NONE, DEEP, NF1), /* DDI1_DDC_SCL */
|
||||
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI0_HPD */
|
||||
PAD_NC(GPP_E15, NONE), /* Not connected */
|
||||
PAD_NC(GPP_E16, NONE), /* Not connected */
|
||||
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DDI0_DDC_SDA */
|
||||
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDI0_DDC_SCL */
|
||||
PAD_NC(GPP_E23, NONE), /* Not connected */
|
||||
|
||||
/* Community 5 - GpioGroup GPP_R */
|
||||
PAD_NC(GPP_R1, NONE), /* Not connected */
|
||||
PAD_NC(GPP_R2, NONE), /* Not connected */
|
||||
PAD_NC(GPP_R3, NONE), /* Not connected */
|
||||
};
|
||||
|
||||
/* Early pad configuration in bootblock */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */
|
||||
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */
|
||||
PAD_CFG_NF(GPP_C2, NONE, DEEP, NF2), /* SMB_ALERT_N */
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF4), /* SIO_UART2_RXD */
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF4), /* SIO_UART2_TXD */
|
||||
};
|
||||
|
||||
const struct pad_config *variant_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(gpio_table);
|
||||
return gpio_table;
|
||||
}
|
||||
|
||||
const struct pad_config *variant_early_gpio_table(size_t *num)
|
||||
{
|
||||
*num = ARRAY_SIZE(early_gpio_table);
|
||||
return early_gpio_table;
|
||||
}
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
#include <gpio.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
static const struct mb_cfg mc_ehl_lpddr4x_memcfg_cfg = {
|
||||
|
||||
.dq_map[DDR_CH0] = {
|
||||
{0xf, 0xf0},
|
||||
{0xf, 0xf0},
|
||||
{0xff, 0x0},
|
||||
{0x0, 0x0},
|
||||
{0x0, 0x0},
|
||||
{0x0, 0x0}
|
||||
},
|
||||
|
||||
.dq_map[DDR_CH1] = {
|
||||
{0xf, 0xf0},
|
||||
{0xf, 0xf0},
|
||||
{0xff, 0x0},
|
||||
{0x0, 0x0},
|
||||
{0x0, 0x0},
|
||||
{0x0, 0x0}
|
||||
},
|
||||
|
||||
/*
|
||||
* The dqs_map arrays map the ddr4 pins to the SoC pins
|
||||
* for both channels.
|
||||
*
|
||||
* the index = pin number on ddr4 part
|
||||
* the value = pin number on SoC
|
||||
*/
|
||||
.dqs_map[DDR_CH0] = {3, 0, 1, 2, 7, 4, 5, 6},
|
||||
.dqs_map[DDR_CH1] = {3, 0, 1, 2, 7, 4, 5, 6},
|
||||
|
||||
/* Baseboard uses 100, 100 and 100 rcomp resistors */
|
||||
.rcomp_resistor = {100, 100, 100},
|
||||
|
||||
.rcomp_targets = {60, 40, 30, 20, 30},
|
||||
|
||||
/* LPDDR4x does not allow interleaved memory */
|
||||
.dq_pins_interleaved = 0,
|
||||
|
||||
/* Baseboard is using config 2 for vref_ca */
|
||||
.vref_ca_config = 2,
|
||||
|
||||
/* Enable Early Command Training */
|
||||
.ect = 1,
|
||||
|
||||
/* Set Board Type */
|
||||
.UserBd = BOARD_TYPE_MOBILE,
|
||||
};
|
||||
|
||||
const struct mb_cfg *variant_memcfg_config(void)
|
||||
{
|
||||
return &mc_ehl_lpddr4x_memcfg_cfg;
|
||||
}
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
23 11 11 0E 15 21 90 08 00 40 00 00 02 22 00 00
|
||||
00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60
|
||||
04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 E1 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
|
||||
20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef MAINBOARD_SPD_H
|
||||
#define MAINBOARD_SPD_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define RCOMP_TARGET_PARAMS 0x5
|
||||
|
||||
void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr);
|
||||
void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr);
|
||||
void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr);
|
||||
void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr);
|
||||
void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr);
|
||||
void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr);
|
||||
#endif
|
||||
Loading…
Reference in New Issue