cpu/x86/mtrr: move cache_ramstage() to its only user
The Intel i3100 northbridge code is the only user of cache_ramstage(). Therefore, place it next to the sole consumer. Change-Id: If15fb8d84f98dce7f4de9e089ec33035622d8f74 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14097 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -20,14 +20,6 @@ void set_var_mtrr(
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}
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#if !IS_ENABLED(CONFIG_CACHE_AS_RAM)
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static void cache_ramstage(void)
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{
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/* Enable caching for lower 1MB and ram stage using variable mtrr */
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disable_cache();
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set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
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enable_cache();
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}
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const int addr_det = 0;
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/* the fixed and variable MTRRs are power-up with random values,
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@ -926,6 +926,13 @@ static void set_receive_enable(const struct mem_controller *ctrl)
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write32(MCBAR+0x154, recenb);
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}
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static void cache_ramstage(void)
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{
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/* Enable caching for lower 1MB and ram stage using variable mtrr */
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disable_cache();
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set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
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enable_cache();
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}
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static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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{
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@ -1189,7 +1196,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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pci_write_config16(ctrl->f0, MCHSCRB, data16);
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/* The memory is now setup, use it */
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#if !CONFIG_CACHE_AS_RAM
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cache_ramstage();
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#endif
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if (!IS_ENABLED(CONFIG_CACHE_AS_RAM))
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cache_ramstage();
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}
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