mb/google/dedede: Create dexi variant
Create the dexi variant of the taranza project by copying the files to a new directory named for the variant. BUG=b:303533815 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_DEXI Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I708a16cb864dca7309cb0201e7887af7456a4885 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78249 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kenneth Chan
Felix Held
parent
90f8151271
commit
2651351805
12 changed files with 509 additions and 0 deletions
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@ -228,6 +228,13 @@ config BOARD_GOOGLE_BOXY
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select RT8168_GET_MAC_FROM_VPD
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select RT8168_SET_LED_MODE
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config BOARD_GOOGLE_DEXI
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select BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
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select RT8168_GEN_ACPI_POWER_RESOURCE
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select RT8168_GET_MAC_FROM_VPD
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select RT8168_SET_LED_MODE
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select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR
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if BOARD_GOOGLE_BASEBOARD_DEDEDE
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config BASEBOARD_DEDEDE_LAPTOP
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@ -300,6 +307,7 @@ config MAINBOARD_PART_NUMBER
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default "Shotzo" if BOARD_GOOGLE_SHOTZO
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default "Taranza" if BOARD_GOOGLE_TARANZA
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default "Boxy" if BOARD_GOOGLE_BOXY
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default "Dexi" if BOARD_GOOGLE_DEXI
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config MAX_CPUS
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int
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@ -342,6 +350,7 @@ config VARIANT_DIR
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default "shotzo" if BOARD_GOOGLE_SHOTZO
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default "taranza" if BOARD_GOOGLE_TARANZA
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default "boxy" if BOARD_GOOGLE_BOXY
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default "dexi" if BOARD_GOOGLE_DEXI
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endif #BOARD_GOOGLE_BASEBOARD_DEDEDE
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@ -91,3 +91,6 @@ config BOARD_GOOGLE_TARANZA
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config BOARD_GOOGLE_BOXY
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bool "-> Boxy"
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config BOARD_GOOGLE_DEXI
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bool "-> Dexi"
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6
src/mainboard/google/dedede/variants/dexi/Makefile.inc
Normal file
6
src/mainboard/google/dedede/variants/dexi/Makefile.inc
Normal file
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@ -0,0 +1,6 @@
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## SPDX-License-Identifier: GPL-2.0-or-later
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ramstage-y += gpio.c
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ramstage-y += variant.c
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ramstage-y += ramstage.c
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93
src/mainboard/google/dedede/variants/dexi/gpio.c
Normal file
93
src/mainboard/google/dedede/variants/dexi/gpio.c
Normal file
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@ -0,0 +1,93 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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/* Pad configuration in ramstage */
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static const struct pad_config gpio_table[] = {
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/* A11 : TOUCH_RPT_EN */
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PAD_NC(GPP_A11, NONE),
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/* A12 : USB_OC1_N */
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PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
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/* A13 : USB_OC2_N */
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PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
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/* A14 : USB_OC3_N */
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PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
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/* A18 : USB_OC0_N */
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PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
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/* B9 : LAN_CLKREQ_ODL */
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PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
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/* D2 : PWM_PP3300_BUZZER */
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PAD_CFG_GPO(GPP_D2, 1, DEEP),
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/* D4 : LAN_PE_ISOLATE_ODL_R */
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PAD_CFG_GPO(GPP_D4, 1, DEEP),
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/* D5 : TOUCH_RESET_L */
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PAD_NC(GPP_D5, NONE),
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/* D6 : EN_PP3300_TOUCH_S0 */
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PAD_NC(GPP_D6, NONE),
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/* D17 : LAN_PERST_L */
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PAD_CFG_GPO(GPP_D17, 1, PLTRST),
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/* D19 : WWAN_WLAN_COEX1 */
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PAD_NC(GPP_D19, NONE),
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/* D20 : WWAN_WLAN_COEX2 */
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PAD_NC(GPP_D20, NONE),
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/* E13 : GPP_E13/DDI0_DDC_SCL */
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PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
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/* E14 : GPP_E14/DDI0_DDC_SDA */
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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/* E15 : GPP_E15/DDI1_DDC_SCL */
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PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1),
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/* E16 : GPP_E16/DDI1_DDC_SDA */
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PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1),
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/* G0 : SD_CMD */
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PAD_NC(GPP_G0, NONE),
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/* G1 : SD_DATA0 */
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PAD_NC(GPP_G1, NONE),
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/* G2 : SD_DATA1 */
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PAD_NC(GPP_G2, NONE),
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/* G3 : SD_DATA2 */
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PAD_NC(GPP_G3, NONE),
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/* G4 : SD_DATA3 */
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PAD_NC(GPP_G4, NONE),
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/* G5 : SD_CD_ODL */
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PAD_NC(GPP_G5, NONE),
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/* G6 : SD_CLK */
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PAD_NC(GPP_G6, NONE),
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/* G7 : SD_SDIO_WP */
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PAD_NC(GPP_G7, NONE),
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/* H4 : AP_I2C_TS_SDA */
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PAD_NC(GPP_H4, NONE),
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/* H5 : AP_I2C_TS_SCL */
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PAD_NC(GPP_H5, NONE),
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/* H6 : AP_I2C_CAM_SDA */
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PAD_NC(GPP_H6, NONE),
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/* H7 : AP_I2C_CAM_SCL */
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PAD_NC(GPP_H7, NONE),
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/* H15 : I2S_SPK_BCLK */
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PAD_NC(GPP_H15, NONE),
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/* R6 : I2S_SPK_LRCK */
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PAD_NC(GPP_R6, NONE),
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/* R7 : I2S_SPK_AUDIO */
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PAD_NC(GPP_R7, NONE),
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/* S2 : DMIC1_CLK */
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PAD_NC(GPP_S2, NONE),
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/* S3 : DMIC1_DATA */
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PAD_NC(GPP_S3, NONE),
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/* S6 : DMIC0_CLK */
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PAD_NC(GPP_S6, NONE),
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/* S7 : DMIC0_DATA */
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PAD_NC(GPP_S7, NONE),
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};
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const struct pad_config *variant_override_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(gpio_table);
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return gpio_table;
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}
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef MAINBOARD_EC_H
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#define MAINBOARD_EC_H
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#include <baseboard/dibbi/ec.h>
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#endif
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@ -0,0 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef MAINBOARD_GPIO_H
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#define MAINBOARD_GPIO_H
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#include <baseboard/gpio.h>
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#endif /* MAINBOARD_GPIO_H */
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@ -0,0 +1,8 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# This is an auto-generated file. Do not edit!!
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# Generated by:
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# ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/dexi/memory/ src/mainboard/google/dedede/variants/dexi/memory/mem_parts_used.txt
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SPD_SOURCES =
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SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B, K4U6E3S4AB-MGCL, H54G46CYRBX267
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SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 1(0b0001) Parts = K4UBE3D4AB-MGCL, H54G56CYRBX247
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@ -0,0 +1,11 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# This is an auto-generated file. Do not edit!!
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# Generated by:
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# ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/dexi/memory/ src/mainboard/google/dedede/variants/dexi/memory/mem_parts_used.txt
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DRAM Part Name ID to assign
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MT53E512M32D1NP-046 WT:B 0 (0000)
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K4U6E3S4AB-MGCL 0 (0000)
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K4UBE3D4AB-MGCL 1 (0001)
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H54G46CYRBX267 0 (0000)
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H54G56CYRBX247 1 (0001)
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@ -0,0 +1,16 @@
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# This is a CSV file containing a list of memory parts used by this variant.
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# One part per line with an optional fixed ID in column 2.
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# Only include a fixed ID if it is required for legacy reasons!
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# Generated IDs are dependent on the order of parts in this file,
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# so new parts must always be added at the end of the file!
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#
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# Generate an updated Makefile.inc and dram_id.generated.txt by running the
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# part_id_gen tool from util/spd_tools.
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# See util/spd_tools/README.md for more details and instructions.
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# Part Name
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MT53E512M32D1NP-046 WT:B
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K4U6E3S4AB-MGCL
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K4UBE3D4AB-MGCL
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H54G46CYRBX267
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H54G56CYRBX247
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304
src/mainboard/google/dedede/variants/dexi/overridetree.cb
Normal file
304
src/mainboard/google/dedede/variants/dexi/overridetree.cb
Normal file
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@ -0,0 +1,304 @@
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chip soc/intel/jasperlake
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| GSPI0 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| | before memory is up |
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#| I2C4 | Audio |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.gspi[0] = {
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.speed_mhz = 1,
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.early_init = 1,
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},
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.i2c[4] = {
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.speed_config[0] = {
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.speed = I2C_SPEED_FAST,
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.scl_lcnt = 190,
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.scl_hcnt = 100,
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.sda_hold = 40,
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}
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},
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}"
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# Power limit config
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register "power_limits_config[JSL_N4500_6W_CORE]" = "{
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.tdp_pl1_override = 6,
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.tdp_pl2_override = 20,
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.tdp_pl4 = 60,
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}"
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register "power_limits_config[JSL_N5100_6W_CORE]" = "{
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.tdp_pl1_override = 6,
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.tdp_pl2_override = 20,
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.tdp_pl4 = 60,
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}"
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# Enable Root Port 3 (index 2) for LAN
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# External PCIe port 7 is mapped to PCIe Root Port 3
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register "PcieRpEnable[2]" = "1"
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register "PcieClkSrcUsage[4]" = "2"
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# Enable Root Port 7 (index 6) for WLAN
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# External PCIe port 3 is mapped to PCIe Root Port 7
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register "PcieRpEnable[6]" = "1"
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register "PcieClkSrcUsage[3]" = "6"
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# Disable PCIe Root Port 8
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register "PcieRpEnable[7]" = "0"
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# Audio related configurations
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register "PchHdaAudioLinkDmicEnable[0]" = "0"
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register "PchHdaAudioLinkDmicEnable[1]" = "0"
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# Disable SD card
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register "sdcard_cd_gpio" = "0"
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register "SdCardPowerEnableActiveHigh" = "0"
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# Disable eDP on port A
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register "DdiPortAConfig" = "0"
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# Enable HPD and DDC for DDI port A
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register "DdiPortAHpd" = "1"
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register "DdiPortADdc" = "1"
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# Does not support external vnn power rail
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register "disable_external_bypass_vr" = "1"
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# USB Port Configuration
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register "usb2_ports[0]" = "{
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.enable = 1,
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.ocpin = OC_SKIP,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_11P25MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-C Port 0
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register "usb2_ports[1]" = "{
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.enable = 1,
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.ocpin = OC1,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_11P25MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port A0
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register "usb2_ports[2]" = "{
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.enable = 1,
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.ocpin = OC2,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_11P25MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port A1
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register "usb2_ports[3]" = "{
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.enable = 1,
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.ocpin = OC3,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_11P25MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port A2
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register "usb2_ports[4]" = "{
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.enable = 1,
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.ocpin = OC0,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_11P25MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port A3
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register "usb2_ports[6]" = "{
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.enable = 1,
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.ocpin = OC_SKIP,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_11P25MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port A4
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A4
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A2
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A3
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# Bitmap for Wake Enable on USB attach/detach
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register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
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USB_PORT_WAKE_ENABLE(2) | \
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USB_PORT_WAKE_ENABLE(3) | \
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USB_PORT_WAKE_ENABLE(4) | \
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USB_PORT_WAKE_ENABLE(5) | \
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USB_PORT_WAKE_ENABLE(7)"
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register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
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USB_PORT_WAKE_ENABLE(2) | \
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USB_PORT_WAKE_ENABLE(3) | \
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USB_PORT_WAKE_ENABLE(4) | \
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USB_PORT_WAKE_ENABLE(5) | \
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USB_PORT_WAKE_ENABLE(6)"
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device domain 0 on
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device pci 04.0 on
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chip drivers/intel/dptf
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## Passive Policy
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 90, 10000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000),
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[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 15000),
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[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 55, 15000)
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}"
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## Critical Policy
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN),
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[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN)
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}"
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 3000,
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.max_power = 6000,
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.time_window_min = 1 * MSECS_PER_SEC,
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.time_window_max = 1 * MSECS_PER_SEC,
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.granularity = 100,
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},
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.pl2 = {
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.min_power = 20000,
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.max_power = 20000,
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.time_window_min = 1 * MSECS_PER_SEC,
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.time_window_max = 1 * MSECS_PER_SEC,
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.granularity = 1000,
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}
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}"
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register "options.tsr[0].desc" = ""Memory""
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register "options.tsr[1].desc" = ""Power""
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register "options.tsr[2].desc" = ""Chassis""
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf" = "{
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[0] = { 255, 3000 },
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[1] = { 24, 1500 },
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[2] = { 16, 1000 },
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[3] = { 8, 500 }
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}"
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device generic 0 on end
|
||||
end
|
||||
end # SA Thermal device
|
||||
device pci 14.0 on
|
||||
chip drivers/usb/acpi
|
||||
device usb 0.0 on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-C Port C0""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 1)"
|
||||
device usb 2.0 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A0""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 2)"
|
||||
device usb 2.1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A1""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 3)"
|
||||
device usb 2.2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A2""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 3)"
|
||||
device usb 2.3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A3""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 2)"
|
||||
device usb 2.4 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Type-A Port A4""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 1)"
|
||||
device usb 2.6 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-C Port C0""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 1)"
|
||||
device usb 3.0 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A4""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 1)"
|
||||
device usb 3.1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A0""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 2)"
|
||||
device usb 3.2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A1""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(2, 3)"
|
||||
device usb 3.3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A3""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 2)"
|
||||
device usb 3.4 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 Type-A Port A2""
|
||||
register "type" = "UPC_TYPE_USB3_A"
|
||||
register "group" = "ACPI_PLD_GROUP(1, 3)"
|
||||
device usb 3.5 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end # USB xHCI
|
||||
device pci 15.0 off end # I2C 0
|
||||
device pci 15.1 off end # I2C 1
|
||||
device pci 15.2 off end # I2C 2
|
||||
device pci 15.3 off end # I2C 3
|
||||
device pci 19.0 on
|
||||
chip drivers/i2c/generic
|
||||
register "hid" = ""RTL5682""
|
||||
register "name" = ""RT58""
|
||||
register "desc" = ""Realtek RT5682""
|
||||
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)"
|
||||
register "property_count" = "1"
|
||||
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
|
||||
register "property_list[0].name" = ""realtek,jd-src""
|
||||
register "property_list[0].integer" = "1"
|
||||
device i2c 1a on end
|
||||
end
|
||||
end # I2C 4
|
||||
device pci 1c.2 on
|
||||
chip drivers/net
|
||||
register "customized_leds" = "0x05af"
|
||||
register "wake" = "GPE0_DW0_03" # GPP_B3
|
||||
register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
|
||||
register "device_index" = "0"
|
||||
device pci 00.0 on end
|
||||
end
|
||||
end # PCI Express Root Port 3 - RTL8111H LAN
|
||||
device pci 1c.6 on
|
||||
chip drivers/wifi/generic
|
||||
register "wake" = "GPE0_DW2_03"
|
||||
device pci 00.0 on end
|
||||
end
|
||||
end # PCI Express Root Port 7 - WLAN
|
||||
device pci 1c.7 off end # PCI Express Root Port 8
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
end
|
||||
end
|
||||
35
src/mainboard/google/dedede/variants/dexi/ramstage.c
Normal file
35
src/mainboard/google/dedede/variants/dexi/ramstage.c
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <baseboard/variants.h>
|
||||
|
||||
/*
|
||||
* Psys_pmax considerations
|
||||
*
|
||||
* Given the hardware design in dexi, the serial shunt resistor is 0.01ohm.
|
||||
* The full scale of hardware PSYS signal 1.6v maps to system current 6.009A
|
||||
* instead of real system power. The equation is shown below:
|
||||
* PSYS = 1.6v ~= (0.01ohm x 6.009A) x 50 (INA213, gain 50V/V) x R631/(R631 + R638)
|
||||
* R631/(R631 + R638) = 0.5325 = 36K / (36K + 31.6K)
|
||||
*
|
||||
* The Psys_pmax is a SW setting which tells IMVP9.1 the mapping between system input
|
||||
* current and the actual system power. Since there is no voltage information
|
||||
* from PSYS, different voltage input would map to different Psys_pmax settings:
|
||||
* For Type-C 15V, the Psys_pmax should be 15v x 6.009A = 90.135W
|
||||
* For Type-C 20V, the Psys_pmax should be 20v x 6.009A = 120.18W
|
||||
* For a barrel jack, the Psys_pmax should be 19v x 6.009A = 114.171W
|
||||
*
|
||||
* Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading,
|
||||
* and the Psys_pmax setting is 120W. Then IMVP9.1 can calculate the current system
|
||||
* power = 120W * 5A / 6.009A = 100W, which is the actual system power.
|
||||
*/
|
||||
const struct psys_config psys_config = {
|
||||
.efficiency = 97,
|
||||
.psys_imax_ma = 6009,
|
||||
.bj_volts_mv = 19000,
|
||||
.bj_power_w = 65,
|
||||
};
|
||||
|
||||
void variant_devtree_update(void)
|
||||
{
|
||||
variant_update_psys_power_limits(&psys_config);
|
||||
}
|
||||
8
src/mainboard/google/dedede/variants/dexi/variant.c
Normal file
8
src/mainboard/google/dedede/variants/dexi/variant.c
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <sar.h>
|
||||
|
||||
const char *get_wifi_sar_cbfs_filename(void)
|
||||
{
|
||||
return "wifi_sar-dexi.hex";
|
||||
}
|
||||
Loading…
Reference in a new issue