soc/intel/cannonlake: Add PrmrrSize and C6DRAM config

This patch ensures coreboot can set PRMRR size and C6DRAM
enable FSP-M UPDs.

Change-Id: I61ec3b6a16e20526516f681ddc3c70755724ed8a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/cannonlake/chip.h

@@ -186,6 +186,14 @@ struct soc_intel_cannonlake_config {
 
 	/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
 	uint8_t eist_enable;
+	/* Enable C6 DRAM */
+	uint8_t enable_c6dram;
+	/*
+	 * PRMRR size setting with below options
+	 * 0x00100000 - 1MiB
+	 * 0x02000000 - 32MiB and beyond
+	 */
+	uint32_t PrmrrSize;
 };
 
 typedef struct soc_intel_cannonlake_config config_t;

src/soc/intel/cannonlake/romstage/romstage.c

@@ -82,6 +82,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
 			mask |= (1 << i);
 	}
 	m_cfg->PcieRpEnableMask = mask;
+	m_cfg->PrmrrSize = config->PrmrrSize;
+	m_cfg->EnableC6Dram = config->enable_c6dram;
 }
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)