From 26886076f40ef92bf2785a9d8363fc4294793644 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 7 Jun 2020 22:19:21 +0200 Subject: [PATCH] nb/intel/haswell: Use PCI bitwise ops Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: I99379299f7e744a3e906bdbc46d55060d9c75d6a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/42153 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/early_init.c | 6 +----- src/northbridge/intel/haswell/minihd.c | 3 +-- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index fb148fab1a..fd188a1af0 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -37,7 +37,6 @@ static void haswell_setup_igd(void) { bool igd_enabled; u16 ggc; - u8 reg8; printk(BIOS_DEBUG, "Initializing IGD...\n"); @@ -59,10 +58,7 @@ static void haswell_setup_igd(void) } /* Enable 256MB aperture */ - reg8 = pci_read_config8(PCI_DEV(0, 2, 0), MSAC); - reg8 &= ~0x06; - reg8 |= 0x02; - pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8); + pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02); } static void start_peg2_link_training(const pci_devfn_t dev) diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index 71ca1e6cf5..c6b5a1257c 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -59,8 +59,7 @@ static void minihd_init(struct device *dev) printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base); /* Set Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Mini-HD configuration */ reg32 = read32(base + 0x100c);