soc/mediatek/common: Reset the watchdog timer before triggering reset

When the watchdog timer reaches 0, the timer value won't reset to the
default value unless there is an external reset or a kick. It will
result in the watchdog failing to trigger the reset signal.

We kick the watchdog to reset the timer to the default value. Also,
because WDT hardware needs about 94us to synchronize the registers,
add a 100us delay before triggering the reset signal.

BUG=b:264003005, b:264017048
BRANCH=corsola
TEST= Reboot successfully with the following cmd
      stop daisydog
      sleep 60 > /dev/watchdog&

Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Signed-off-by: Kuan-Hsun Cheng <allen-kh.cheng@mediatek.com>
Change-Id: Ic4964103d54910c4a1e675b59c362e93c2213b19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71754
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/mediatek/common/include/soc/wdt_common.h

@@ -32,6 +32,11 @@ enum {
 	MTK_WDT_MODE_ENABLE	= 1 << 0
 };
 
+/* WDT_RESTART */
+enum {
+	MTK_WDT_RESTART_KEY	= 0x1971
+};
+
 /* WDT_RESET */
 enum {
 	MTK_WDT_SWRST_KEY	= 0x1209,

src/soc/mediatek/common/wdt.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <arch/cache.h>
+#include <delay.h>
 #include <device/mmio.h>
 #include <console/console.h>
 #include <halt.h>
@@ -23,7 +24,9 @@ static inline void mtk_wdt_swreset(void)
 	printk(BIOS_INFO, "%s() called!\n", __func__);
 
 	dcache_clean_all();
+	write32(&mtk_wdt->wdt_restart, MTK_WDT_RESTART_KEY);
 	setbits32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
+	udelay(100);
 	write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
 
 	halt();