mb/google/hatch: Enable wake from trackpad
For some reason, wake does not currently work from GPP_D21, but IRQs are working fine from that gpio. Thus, we have to switch IRQ to GPP_D21 and wake to GPP_A21, which was previously used for IRQs from the trackpad. Additionally, we need to use two gpios for irqs and wake source at the moment because of b:123967687, where FSP is locking down PCR and configuring ITSS. We need to configure the wake source gpio as inverted and the IRQ gpio as non-inverted until the bug is resolved. BUG=b:121212459 BRANCH=None TEST=run evtest with trackpad Use trackpad with ChromeOS UI and make sure it reacts as expected. Run powerd_dbus_suspend and press trackpad and make sure DUT wakes. Change-Id: I7b236136befc05c6586d9ba69185ed4b5d385273 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/31533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -200,7 +200,8 @@ chip soc/intel/cannonlake
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chip drivers/i2c/generic
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register "hid" = ""ELAN0000""
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register "desc" = ""ELAN Touchpad""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A21_IRQ)"
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)"
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register "wake" = "GPE0_DW0_21"
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device i2c 15 on end
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end
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end # I2C #0
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@ -28,11 +28,11 @@ static const struct pad_config gpio_table[] = {
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/* WWAN_RADIO_DISABLE_1V8_ODL */
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PAD_CFG_GPO(GPP_A19, 1, DEEP),
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/*
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* TRACKPAD_INT_ODL
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* TODO Configure it back to invert mode, when
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* ITSS IPCx configuration is fixed in FSP.
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* TRACKPAD_INT_ODL (wake)
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* TODO Combine into single gpio, when ITSS IPCx configuration
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* is fixed in FSP.
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*/
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PAD_CFG_GPI_APIC(GPP_A21, NONE, PLTRST, LEVEL, NONE),
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PAD_CFG_GPI_SCI(GPP_A21, NONE, DEEP, EDGE_SINGLE, INVERT),
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/* SRCCLKREQ1 */
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
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/* PCIE_14_WLAN_CLKREQ_ODL */
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@ -97,6 +97,12 @@ static const struct pad_config gpio_table[] = {
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* ITSS IPCx configuration is fixed in FSP.
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*/
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PAD_CFG_GPI_APIC(GPP_D16, NONE, DEEP, LEVEL, NONE),
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/*
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* TRACKPAD_INT_ODL
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* TODO Combine into single gpio with invert mode, when ITSS
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* IPCx configuration is fixed in FSP.
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*/
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PAD_CFG_GPI_APIC(GPP_D21, NONE, PLTRST, LEVEL, NONE),
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/* SATAGP1 */
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PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2),
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/* M2_SSD_PE_WAKE_ODL */
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