AGESA: Fix SSE regression and align stack early

When allowing use of SSE instructions, stack must be
aligned to 16 bytes. Adjust x86 entry to C accordingly,
by pushing values to maintain the alignment.

Fixes regression with new toolchain using GCC-6.3 and
  ec0a393 console: Enable printk for ENV_LIBAGESA

For some builds, the above-mentioned commit emitted
SSE instruction 'andps (%esp),%xmm0' with incorrectly
aligned esp, raising exception and thus preventing boot.

Change-Id: Ief57a2ea053c7497d50903838310b7f7800bff26
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18622
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/cpu/amd/agesa/cache_as_ram.inc

@@ -63,6 +63,9 @@ cache_as_ram_setup:
 
   AMD_ENABLE_STACK
 
+  /* Align the stack. */
+  and     $0xFFFFFFF0, %esp
+
 #ifdef __x86_64__
   /* switch to 64 bit long mode */
   mov     %esi, %ecx
@@ -111,8 +114,6 @@ cache_as_ram_setup:
   /* Pass the BIST result */
   cvtsd2si        %xmm0, %edi
 
-  /* align the stack */
-  and     $0xFFFFFFF0, %esp
 
   .code64
   call    cache_as_ram_main
@@ -126,6 +127,9 @@ cache_as_ram_setup:
   /* Restore the  cpu_init_detected */
   cvtsd2si  %xmm1, %ebx
 
+  /* Must maintain 16-byte stack alignment here. */
+  pushl $0x0
+  pushl $0x0
   pushl %ebx  /* init detected */
   pushl %edx  /* bist */
   call  cache_as_ram_main