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mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes 

Since mc_ehl4 was only a copy of mc_ehl1 in a first step, the default
value of the Kconfig switch EARLY_PCI_BRIDGE_FUNCTION must be set to
'0'. On this mainboard NC FPGA is connected to PCIe root port #1
(00:1c.0).

Change-Id: I15035523d8575d486c3f2d0ffe3916712ee89d7d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Mario Scheithauer 2023-04-04 13:35:38 +02:00 committed by Felix Held
parent ae5852bd7b
commit 26ad425728
1 changed files with 1 additions and 1 deletions
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src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig
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@ -22,7 +22,7 @@ config EARLY_PCI_BRIDGE_DEVICE
config EARLY_PCI_BRIDGE_FUNCTION
hex
depends on NC_FPGA_POST_CODE
default 0x2
default 0x0
config EARLY_PCI_MMIO_BASE
hex