remove more warnings.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -92,7 +92,7 @@ pcideadlock(void)
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*
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****************************************************************************/
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void bug784(void)
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static void bug784(void)
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{
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msr_t msr;
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//static char *name = "Geode by NSC";
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@ -133,7 +133,7 @@ void bug784(void)
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* Modified:
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*
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**************************************************************************/
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void eng1398(void)
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static void eng1398(void)
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{
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msr_t msr;
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@ -164,7 +164,7 @@ void eng1398(void)
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* Modified:
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*
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**************************************************************************/
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void
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static void
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eng2900(void)
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{
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msr_t msr;
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@ -248,7 +248,7 @@ eng2900(void)
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}
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}
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void bug118253(void)
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static void bug118253(void)
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{
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/* GLPCI PIO Post Control shouldn't be enabled */
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msr_t msr;
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@ -258,7 +258,7 @@ void bug118253(void)
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wrmsr(GLPCI_SPARE, msr);
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}
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void bug118339(void)
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static void bug118339(void)
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{
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/* per AMD, do this always */
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msr_t msr = {0,0};
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@ -337,7 +337,7 @@ void bug118339(void)
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/** Modified:*/
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/***/
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/****************************************************************************/
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void disablememoryreadorder(void)
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static void disablememoryreadorder(void)
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{
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msr_t msr;
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msr = rdmsr(MC_CF8F_DATA);
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@ -353,7 +353,7 @@ typedef struct {
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*
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* ---------------------------------------------------------------------------------------
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*/
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BOOL (*AMD_CB_CustomizeTrafficDistribution)();
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BOOL (*AMD_CB_CustomizeTrafficDistribution)( void );
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/**----------------------------------------------------------------------------------------
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@ -1041,7 +1041,7 @@ void ht3SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 t
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/**----------------------------------------------------------------------------------------
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*
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* void
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* static void
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* ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb)
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*
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* Description:
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@ -1058,7 +1058,7 @@ void ht3SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 t
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*
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* ---------------------------------------------------------------------------------------
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*/
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void ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb)
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static void ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb)
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{
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u8 curNode;
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SBDFO linkBase;
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@ -704,7 +704,6 @@ RCONFInit(void)
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int i;
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msr_t msr;
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uint8_t SysMemCacheProp;
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uint8_t RegionProp;
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/* Locate SYSMEM entry in GLIU0table */
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for(i = 0; gliu0table[i].desc_name != GL_END; i++) {
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@ -17,6 +17,10 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef CONFIG_NORTHBRIDGE_AMD_AMDFAM10
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#define CONFIG_NORTHBRIDGE_AMD_AMDFAM10 0
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#endif
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#include "rs780_rev.h"
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#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
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@ -142,7 +146,7 @@ static void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
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}
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}
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static void get_cpu_rev()
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static void get_cpu_rev(void)
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{
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u32 eax;
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@ -168,17 +172,17 @@ static void get_cpu_rev()
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printk(BIOS_INFO, "CPU Rev is K8_10.\n");
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}
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static u8 is_famly10()
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static u8 is_famly10(void)
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{
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return (cpuid_eax(1) & 0xff00000) != 0;
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}
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static u8 l3_cache()
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static u8 l3_cache(void)
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{
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return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0;
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}
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static u8 cpu_core_number()
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static u8 cpu_core_number(void)
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{
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return (cpuid_ecx(0x80000008) & 0xFF) + 1;
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}
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@ -226,7 +230,7 @@ static const u8 rs780_ibias[] = {
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[0xe] = 0xC6, /* 2.6Ghz HyperTransport 3 only */
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};
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static void rs780_htinit()
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static void rs780_htinit(void)
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{
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/*
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* About HT, it has been done in enumerate_ht_chain().
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@ -325,7 +329,7 @@ static void rs780_htinit()
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* Function2: DRAM and HT technology Trace mode configuration
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* Function3: Miscellaneous configuration
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*******************************************************/
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static void k8_optimization()
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static void k8_optimization(void)
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{
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device_t k8_f0, k8_f2, k8_f3;
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msr_t msr;
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@ -367,7 +371,7 @@ static void k8_optimization()
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#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 */
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#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */
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void fam10_optimization()
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void fam10_optimization(void)
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{
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device_t cpu_f0, cpu_f2, cpu_f3;
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msr_t msr;
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