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remove more warnings. 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-04-02 22:31:35 +00:00 committed by Stefan Reinauer
parent b4a3fcfb4b
commit 26afd18e10
5 changed files with 20 additions and 17 deletions
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12
src/cpu/amd/model_gx2/cpubug.c
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@ -92,7 +92,7 @@ pcideadlock(void)
* *
****************************************************************************/ ****************************************************************************/
void bug784(void) static void bug784(void)
{ {
msr_t msr; msr_t msr;
//static char *name = "Geode by NSC"; //static char *name = "Geode by NSC";
@ -133,7 +133,7 @@ void bug784(void)
* Modified: * Modified:
* *
**************************************************************************/ **************************************************************************/
void eng1398(void) static void eng1398(void)
{ {
msr_t msr; msr_t msr;
@ -164,7 +164,7 @@ void eng1398(void)
* Modified: * Modified:
* *
**************************************************************************/ **************************************************************************/
void static void
eng2900(void) eng2900(void)
{ {
msr_t msr; msr_t msr;
@ -248,7 +248,7 @@ eng2900(void)
} }
} }
void bug118253(void) static void bug118253(void)
{ {
/* GLPCI PIO Post Control shouldn't be enabled */ /* GLPCI PIO Post Control shouldn't be enabled */
msr_t msr; msr_t msr;
@ -258,7 +258,7 @@ void bug118253(void)
wrmsr(GLPCI_SPARE, msr); wrmsr(GLPCI_SPARE, msr);
} }
void bug118339(void) static void bug118339(void)
{ {
/* per AMD, do this always */ /* per AMD, do this always */
msr_t msr = {0,0}; msr_t msr = {0,0};
@ -337,7 +337,7 @@ void bug118339(void)
/** Modified:*/ /** Modified:*/
/***/ /***/
/****************************************************************************/ /****************************************************************************/
void disablememoryreadorder(void) static void disablememoryreadorder(void)
{ {
msr_t msr; msr_t msr;
msr = rdmsr(MC_CF8F_DATA); msr = rdmsr(MC_CF8F_DATA);

2
src/northbridge/amd/amdht/h3finit.h
View File

@ -353,7 +353,7 @@ typedef struct {
* *
* --------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------
*/ */
BOOL (*AMD_CB_CustomizeTrafficDistribution)(); BOOL (*AMD_CB_CustomizeTrafficDistribution)( void );
/**---------------------------------------------------------------------------------------- /**----------------------------------------------------------------------------------------

4
src/northbridge/amd/amdht/h3ncmn.c
View File

@ -1041,7 +1041,7 @@ void ht3SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 t
/**---------------------------------------------------------------------------------------- /**----------------------------------------------------------------------------------------
* *
* void * static void
* ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb) * ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb)
* *
* Description: * Description:
@ -1058,7 +1058,7 @@ void ht3SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 t
* *
* --------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------
*/ */
void ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb) static void ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb)
{ {
u8 curNode; u8 curNode;
SBDFO linkBase; SBDFO linkBase;

1
src/northbridge/amd/gx2/northbridgeinit.c
View File

@ -704,7 +704,6 @@ RCONFInit(void)
int i; int i;
msr_t msr; msr_t msr;
uint8_t SysMemCacheProp; uint8_t SysMemCacheProp;
uint8_t RegionProp;
/* Locate SYSMEM entry in GLIU0table */ /* Locate SYSMEM entry in GLIU0table */
for(i = 0; gliu0table[i].desc_name != GL_END; i++) { for(i = 0; gliu0table[i].desc_name != GL_END; i++) {

18
src/southbridge/amd/rs780/rs780_early_setup.c
View File

@ -17,6 +17,10 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#ifndef CONFIG_NORTHBRIDGE_AMD_AMDFAM10
#define CONFIG_NORTHBRIDGE_AMD_AMDFAM10 0
#endif
#include "rs780_rev.h" #include "rs780_rev.h"
#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
@ -142,7 +146,7 @@ static void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
} }
} }
static void get_cpu_rev() static void get_cpu_rev(void)
{ {
u32 eax; u32 eax;
@ -168,17 +172,17 @@ static void get_cpu_rev()
printk(BIOS_INFO, "CPU Rev is K8_10.\n"); printk(BIOS_INFO, "CPU Rev is K8_10.\n");
} }
static u8 is_famly10() static u8 is_famly10(void)
{ {
return (cpuid_eax(1) & 0xff00000) != 0; return (cpuid_eax(1) & 0xff00000) != 0;
} }
static u8 l3_cache() static u8 l3_cache(void)
{ {
return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0; return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0;
} }
static u8 cpu_core_number() static u8 cpu_core_number(void)
{ {
return (cpuid_ecx(0x80000008) & 0xFF) + 1; return (cpuid_ecx(0x80000008) & 0xFF) + 1;
} }
@ -226,7 +230,7 @@ static const u8 rs780_ibias[] = {
[0xe] = 0xC6, /* 2.6Ghz HyperTransport 3 only */ [0xe] = 0xC6, /* 2.6Ghz HyperTransport 3 only */
}; };
static void rs780_htinit() static void rs780_htinit(void)
{ {
/* /*
* About HT, it has been done in enumerate_ht_chain(). * About HT, it has been done in enumerate_ht_chain().
@ -325,7 +329,7 @@ static void rs780_htinit()
* Function2: DRAM and HT technology Trace mode configuration * Function2: DRAM and HT technology Trace mode configuration
* Function3: Miscellaneous configuration * Function3: Miscellaneous configuration
*******************************************************/ *******************************************************/
static void k8_optimization() static void k8_optimization(void)
{ {
device_t k8_f0, k8_f2, k8_f3; device_t k8_f0, k8_f2, k8_f3;
msr_t msr; msr_t msr;
@ -367,7 +371,7 @@ static void k8_optimization()
#endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 */ #endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 */
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */ #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */
void fam10_optimization() void fam10_optimization(void)
{ {
device_t cpu_f0, cpu_f2, cpu_f3; device_t cpu_f0, cpu_f2, cpu_f3;
msr_t msr; msr_t msr;