soc/intel/broadwell: Fix spacing issues detected by checkpatch
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
ERROR: space required after that ',' (ctx:VxV)
ERROR: space prohibited before that ',' (ctx:WxW)
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: spaces required around that '<=' (ctx:WxV)
ERROR: spaces required around that '<=' (ctx:VxV)
ERROR: spaces required around that '>' (ctx:VxV)
ERROR: spaces required around that '>=' (ctx:VxV)
ERROR: spaces required around that '+=' (ctx:VxV)
ERROR: spaces required around that '<' (ctx:VxV)
ERROR: "foo * bar" should be "foo *bar"
ERROR: "foo* bar" should be "foo *bar"
ERROR: "(foo*)" should be "(foo *)"
ERROR: space required before the open parenthesis '('
WARNING: space prohibited between function name and open parenthesis '('
WARNING: please, no space before tabs
WARNING: please, no spaces at the start of a line
False positives are generated for the following test:
WARNING: space prohibited between function name and open parenthesis '('
in both pei_data.h and pei_wrapper.h
TEST=None
Change-Id: Icab08e5fcb6d5089902ae5ec2aa5bbee5ac432ed
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18872
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Lee Leahy
parent
7504268318
commit
26b7cd0fa8
21 changed files with 105 additions and 105 deletions
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@ -74,12 +74,12 @@ static acpi_cstate_t cstate_map[NUM_C_STATES] = {
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[C_STATE_C1] = {
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.latency = 0,
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.power = 1000,
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.resource = MWAIT_RES(0,0),
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.resource = MWAIT_RES(0, 0),
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},
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[C_STATE_C1E] = {
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.latency = 0,
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.power = 1000,
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.resource = MWAIT_RES(0,1),
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.resource = MWAIT_RES(0, 1),
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},
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[C_STATE_C3] = {
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.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
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@ -185,7 +185,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
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#endif
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}
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void acpi_create_intel_hpet(acpi_hpet_t * hpet)
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void acpi_create_intel_hpet(acpi_hpet_t *hpet)
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{
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acpi_header_t *header = &(hpet->header);
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acpi_addr_t *addr = &(hpet->addr);
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@ -543,28 +543,28 @@ void generate_cpu_entries(device_t device)
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printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
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numcpus, cores_per_package);
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for (cpuID=1; cpuID <=numcpus; cpuID++) {
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for (coreID=1; coreID<=cores_per_package; coreID++) {
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if (coreID>1) {
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for (cpuID = 1; cpuID <= numcpus; cpuID++) {
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for (coreID = 1; coreID <= cores_per_package; coreID++) {
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if (coreID > 1) {
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pcontrol_blk = 0;
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plen = 0;
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}
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/* Generate processor \_PR.CPUx */
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acpigen_write_processor(
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(cpuID-1)*cores_per_package+coreID-1,
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(cpuID - 1) * cores_per_package+coreID - 1,
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pcontrol_blk, plen);
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/* Generate P-state tables */
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generate_P_state_entries(
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coreID-1, cores_per_package);
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coreID - 1, cores_per_package);
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/* Generate C-state tables */
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generate_C_state_entries();
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/* Generate T-state tables */
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generate_T_state_entries(
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cpuID-1, cores_per_package);
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cpuID - 1, cores_per_package);
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acpigen_pop_len();
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}
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@ -17,17 +17,17 @@
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#define _BROADWELL_PCI_DEVS_H_
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#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
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#define _PCH_DEVFN(slot,func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
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#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
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#if defined(__PRE_RAM__) || defined(__SMM__) || defined(__ROMCC__)
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#include <arch/io.h>
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#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
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#define _PCH_DEV(slot,func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
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#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
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#else
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#include <device/device.h>
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#include <device/pci_def.h>
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#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot))
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#define _PCH_DEV(slot,func) dev_find_slot(0, _PCH_DEVFN(slot, func))
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#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func))
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#endif
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/* System Agent Devices */
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@ -35,9 +35,9 @@
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/* Root Port configuration space hide */
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#define RPFN_HIDE(port) (1 << (((port) * 4) + 3))
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/* Get the function number assigned to a Root Port */
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#define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7)
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#define RPFN_FNGET(reg, port) (((reg) >> ((port) * 4)) & 7)
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/* Set the function number for a Root Port */
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#define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4))
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#define RPFN_FNSET(port, func) (((func) & 7) << ((port) * 4))
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/* Root Port function number mask */
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#define RPFN_FNMASK(port) (7 << ((port) * 4))
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@ -135,7 +135,7 @@
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#define SOFT_RESET_CTRL 0x38f4
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#define SOFT_RESET_DATA 0x38f8
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#define DIR_ROUTE(a,b,c,d) \
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#define DIR_ROUTE(a, b, c, d) \
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(((d) << DIR_IDR) | ((c) << DIR_ICR) | \
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((b) << DIR_IBR) | ((a) << DIR_IAR))
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@ -106,7 +106,7 @@ static void pch_pirq_init(device_t dev)
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pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
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for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
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u8 int_pin=0, int_line=0;
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u8 int_pin = 0, int_line = 0;
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if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
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continue;
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@ -133,7 +133,7 @@ static void pch_power_options(device_t dev)
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const char *state;
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
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int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
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/* Which state do we want to goto after g3 (power restored)?
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* 0 == S0 Full On
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@ -591,7 +591,7 @@ static void southcluster_inject_dsdt(device_t device)
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gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
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if (!gnvs) {
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gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs));
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gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
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if (gnvs)
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memset(gnvs, 0, sizeof(*gnvs));
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}
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@ -88,7 +88,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
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}
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}
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#else
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# define mei_dump(ptr,dword,offset,type) do {} while (0)
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# define mei_dump(ptr, dword, offset, type) do {} while (0)
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#endif
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/*
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@ -616,7 +616,7 @@ static void intel_me_finalize(device_t dev)
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u32 reg32;
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/* S3 path will have hidden this device already */
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if (!mei_base_address || mei_base_address == (u8*) 0xfffffff0)
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if (!mei_base_address || mei_base_address == (u8 *) 0xfffffff0)
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return;
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/* Make sure IO is disabled */
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@ -921,7 +921,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev)
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}
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#endif
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#define ASSIGN_FIELD_PTR(field_,val_) \
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#define ASSIGN_FIELD_PTR(field_, val_) \
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{ \
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mbp_data->field_ = (typeof(mbp_data->field_))(void *)val_; \
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break; \
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@ -931,7 +931,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev)
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for (i = 0; i < mbp->header.mbp_size - 1;) {
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mbp_item_header *item = (void *)&mbp->data[i];
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switch(MBP_MAKE_IDENT(item->app_id, item->item_id)) {
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switch (MBP_MAKE_IDENT(item->app_id, item->item_id)) {
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case MBP_IDENT(KERNEL, FW_VER):
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ASSIGN_FIELD_PTR(fw_version_name, &mbp->data[i+1]);
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@ -37,7 +37,7 @@ static void print_status_bits(u32 status, const char *bit_names[])
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if (!status)
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return;
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for (i=31; i>=0; i--) {
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for (i = 31; i >= 0; i--) {
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if (status & (1 << i)) {
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if (bit_names[i])
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printk(BIOS_DEBUG, "%s ", bit_names[i]);
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@ -55,7 +55,7 @@ static void print_gpio_status(u32 status, int start)
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if (!status)
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return;
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for (i=31; i>=0; i--) {
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for (i = 31; i >= 0; i--) {
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if (status & (1 << i))
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printk(BIOS_DEBUG, "GPIO%d ", start + i);
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}
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@ -43,7 +43,7 @@
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void raminit(struct pei_data *pei_data)
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{
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struct region_device rdev;
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struct memory_info* mem_info;
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struct memory_info *mem_info;
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pei_wrapper_entry_t entry;
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int ret;
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@ -99,7 +99,7 @@ void raminit(struct pei_data *pei_data)
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/* Print the MRC version after executing the UEFI PEI stage. */
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u32 version = MCHBAR32(MCHBAR_PEI_VERSION);
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printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n",
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version >> 24 , (version >> 16) & 0xff,
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version >> 24, (version >> 16) & 0xff,
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(version >> 8) & 0xff, version & 0xff);
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report_memory_config();
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@ -98,7 +98,7 @@ static void report_cpu_info(void)
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if (cpuidr.eax < 0x80000004) {
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strcpy(cpu_string, "Platform info not available");
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} else {
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u32 *p = (u32*) cpu_string;
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u32 *p = (u32 *)cpu_string;
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for (i = 2; i <= 4 ; i++) {
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cpuidr = cpuid(index + i);
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*p++ = cpuidr.eax;
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@ -38,7 +38,7 @@
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#include <vendorcode/google/chromeos/chromeos.h>
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/* Entry from cache-as-ram.inc. */
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void * asmlinkage romstage_main(unsigned long bist,
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asmlinkage void *romstage_main(unsigned long bist,
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uint32_t tsc_low, uint32_t tsc_hi)
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{
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struct romstage_params rp = {
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@ -27,7 +27,7 @@
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static int early_spi_read_block(u32 offset, u8 size, u8 *buffer)
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{
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u32 *ptr32 = (u32*)buffer;
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u32 *ptr32 = (u32 *)buffer;
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u32 i;
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/* Clear status bits */
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@ -76,13 +76,13 @@ static int early_spi_read_block(u32 offset, u8 size, u8 *buffer)
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}
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/* Read the data */
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for (i = 0; i < size; i+=sizeof(u32)) {
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for (i = 0; i < size; i += sizeof(u32)) {
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if (size-i >= 4) {
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/* reading >= dword */
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*ptr32++ = SPIBAR32(SPIBAR_FDATA(i/sizeof(u32)));
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} else {
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/* reading < dword */
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u8 j, *ptr8 = (u8*)ptr32;
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u8 j, *ptr8 = (u8 *)ptr32;
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u32 temp = SPIBAR32(SPIBAR_FDATA(i/sizeof(u32)));
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for (j = 0; j < (size-i); j++) {
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*ptr8++ = temp & 0xff;
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@ -301,11 +301,11 @@ static void southbridge_smi_gsmi(void)
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return;
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/* Command and return value in EAX */
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ret = (u32*)&io_smi->rax;
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ret = (u32 *)&io_smi->rax;
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sub_command = (u8)(*ret >> 8);
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/* Parameter buffer in EBX */
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param = (u32*)&io_smi->rbx;
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param = (u32 *)&io_smi->rbx;
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/* drivers/elog/gsmi.c */
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*ret = gsmi_exec(sub_command, param);
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@ -473,7 +473,7 @@ static void southbridge_smi_monitor(void)
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RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
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trap_cycle = RCBA32(0x1e10);
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for (i=16; i<20; i++) {
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for (i = 16; i < 20; i++) {
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if (trap_cycle & (1 << i))
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mask |= (0xff << ((i - 16) << 2));
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}
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@ -504,7 +504,7 @@ static void southbridge_smi_monitor(void)
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printk(BIOS_DEBUG, " trapped io address = 0x%x\n",
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trap_cycle & 0xfffc);
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for (i=0; i < 4; i++)
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for (i = 0; i < 4; i++)
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if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
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printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
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printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
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