Intel e7505: handlers for undocumented registers
Makes the code a bit more readable, IMO. There is no clean way to implement this as the affected registers are undocumented. Seems ROMCC cannot handle the enum. Also any of my future changes would not be even abuild tested as there is no longer a board with ROMCC and this chipset. E7505 chipset is CAR only from now on. Change-Id: I0e2d8ba0c7ed7cce46d9eafb8d8badf04cf75f7a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/895 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Kyösti Mälkki
Patrick Georgi
parent
ad8c95f03b
commit
26c7b86907
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@ -486,51 +486,109 @@ static inline void local_mdelay(int i)
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#define EXTRA_DELAY DO_DELAY
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/*-----------------------------------------------------------------------------
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Handle (undocumented) control bits in device 0:6.0
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Handle (undocumented) control bits MCHTST and PCI_DEV(0,6,0)
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-----------------------------------------------------------------------------*/
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typedef enum {
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MCHTST_CMD_0,
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D060_ENABLE,
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D060_DISABLE,
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RCOMP_BAR_ENABLE,
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RCOMP_BAR_DISABLE,
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} mchtst_cc;
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typedef enum {
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D060_CMD_0,
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D060_CMD_1,
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} d060_cc;
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typedef enum {
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RCOMP_HOLD,
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RCOMP_RELEASE,
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RCOMP_SMR_00,
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RCOMP_SMR_01,
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} rcomp_smr_cc;
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/**
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* MCHTST - 0xF4 - 0xF7 -- Based on similarity to 855PM
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*
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* [31:31] Purpose unknown
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* [30:30] Purpose unknown
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* [29:23] Unknown - not used?
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* [22:22] System Memory MMR Enable
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* 0 == Disable: mem space and BAR at 0x14 are not accessible
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* 1 == Enable: mem space and BAR at 0x14 are accessible
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* [21:20] Purpose unknown
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* [19:02] Unknown - not used?
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* [01:01] D6EN (Device #6 enable)
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* 0 == Disable
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* 1 == Enable
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* [00:00] Unknown - not used?
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*/
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static inline void mchtest_control(mchtst_cc cmd)
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{
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uint32_t dword = pci_read_config32(MCHDEV, MCHTST);
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switch (cmd) {
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case MCHTST_CMD_0:
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dword &= ~(3 << 30);
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break;
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case RCOMP_BAR_ENABLE:
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dword |= (1 << 22);
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break;
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case RCOMP_BAR_DISABLE:
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dword &= ~(1 << 22);
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break;
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case D060_ENABLE:
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dword |= (1 << 1);
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break;
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case D060_DISABLE:
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dword &= ~(1 << 1);
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break;
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};
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pci_write_config32(MCHDEV, MCHTST, dword);
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}
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/**
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*
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*/
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static void ram_handle_d060_1(void)
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static inline void d060_control(d060_cc cmd)
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{
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uint32_t dword;
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dword = pci_read_config32(MCHDEV, MCHTST);
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dword |= 0x02;
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pci_write_config32(MCHDEV, MCHTST, dword);
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dword = pci_read_config32(D060DEV, 0xf0);
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dword |= 0x04;
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mchtest_control(D060_ENABLE);
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uint32_t dword = pci_read_config32(D060DEV, 0xf0);
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switch (cmd) {
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case D060_CMD_0:
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dword |= (1 << 2);
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break;
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case D060_CMD_1:
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dword |= (3 << 27);
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break;
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}
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pci_write_config32(D060DEV, 0xf0, dword);
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dword = pci_read_config32(MCHDEV, MCHTST);
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dword &= ~0x02;
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pci_write_config32(MCHDEV, MCHTST, dword);
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mchtest_control(D060_DISABLE);
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}
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/**
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*
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*/
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static void ram_handle_d060_2(void)
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static inline void rcomp_smr_control(rcomp_smr_cc cmd)
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{
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uint32_t dword;
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uint8_t revision;
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revision = pci_read_config8(MCHDEV, 0x08);
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if (revision >= 3) {
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dword = pci_read_config32(MCHDEV, MCHTST);
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dword |= 0x02;
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pci_write_config32(MCHDEV, MCHTST, dword);
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dword = pci_read_config32(D060DEV, 0xf0);
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dword |= 0x18000000;
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pci_write_config32(D060DEV, 0xf0, dword);
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dword = pci_read_config32(MCHDEV, MCHTST);
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dword &= ~0x02;
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pci_write_config32(MCHDEV, MCHTST, dword);
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uint32_t dword = read32(RCOMP_MMIO + SMRCTL);
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switch (cmd) {
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case RCOMP_HOLD:
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dword |= (1 << 9);
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break;
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case RCOMP_RELEASE:
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dword &= ~((1 << 9) | (3 << 0));
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dword |= (1 << 10) | (1 << 0);
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break;
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case RCOMP_SMR_00:
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dword &= ~(1 << 8);
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break;
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case RCOMP_SMR_01:
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dword |= (1 << 10) | (1 << 8);
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break;
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}
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write32(RCOMP_MMIO + SMRCTL, dword);
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}
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/*-----------------------------------------------------------------------------
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@ -1771,18 +1829,12 @@ static void ram_set_rcomp_regs(void)
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RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n");
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/*enable access to the rcomp bar */
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dword = pci_read_config32(MCHDEV, MCHTST);
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dword |= (1 << 22);
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pci_write_config32(MCHDEV, MCHTST, dword);
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// Set the RCOMP MMIO base address
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/* Set the RCOMP MMIO base address */
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mchtest_control(RCOMP_BAR_ENABLE);
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pci_write_config32(MCHDEV, SMRBASE, RCOMP_MMIO);
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// Block RCOMP updates while we configure the registers
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dword = read32(RCOMP_MMIO + SMRCTL);
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dword |= (1 << 9);
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write32(RCOMP_MMIO + SMRCTL, dword);
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/* Block RCOMP updates while we configure the registers */
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rcomp_smr_control(RCOMP_HOLD);
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/* Begin to write the RCOMP registers */
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write8(RCOMP_MMIO + 0x2c, 0x0);
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@ -1859,36 +1911,23 @@ static void ram_set_rcomp_regs(void)
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dword &= 0x7f7fffff;
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write32(RCOMP_MMIO + 0x408, dword);
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ram_handle_d060_1();
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dword = pci_read_config32(MCHDEV, MCHTST);
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dword &= 0x3fffffff;
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pci_write_config32(MCHDEV, MCHTST, dword);
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d060_control(D060_CMD_0);
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mchtest_control(MCHTST_CMD_0);
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revision = pci_read_config8(MCHDEV, 0x08);
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if (revision >= 3) {
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dword = read32(RCOMP_MMIO + SMRCTL);
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dword &= ~0x100;
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write32(RCOMP_MMIO + SMRCTL, dword);
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dword = read32(RCOMP_MMIO + SMRCTL);
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dword |= 0x500;
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write32(RCOMP_MMIO + SMRCTL, dword);
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rcomp_smr_control(RCOMP_SMR_00);
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rcomp_smr_control(RCOMP_SMR_01);
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}
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dword = read32(RCOMP_MMIO + SMRCTL);
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dword &= ~0x203;
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dword |= 0x401;
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write32(RCOMP_MMIO + SMRCTL, dword);
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rcomp_smr_control(RCOMP_RELEASE);
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/* Wait 40 usec */
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SLOW_DOWN_IO;
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// Clear the RCOMP MMIO base address
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/* Clear the RCOMP MMIO base address */
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pci_write_config32(MCHDEV, SMRBASE, 0);
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/*disable access to the rcomp bar */
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dword = pci_read_config32(MCHDEV, MCHTST);
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dword &= ~(1 << 22);
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pci_write_config32(MCHDEV, MCHTST, dword);
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mchtest_control(RCOMP_BAR_DISABLE);
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}
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/*-----------------------------------------------------------------------------
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@ -2050,7 +2089,10 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
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ram_set_rcomp_regs();
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ram_set_d0f0_regs();
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ram_handle_d060_2();
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uint8_t revision = pci_read_config8(MCHDEV, 0x08);
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if (revision >= 3)
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d060_control(D060_CMD_1);
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}
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/**
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