i945: Replace video gfx init.
Old init was a replay not even meant to have been committed. This one really computes values and does its job. Tested on Macbook2,1 (1280x800) and X60 (1024x768). Change-Id: I61b6946c095fe06e20ae9a0db54696d0568225dd Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5320 Reviewed-by: Francis Rowe <info@gluglug.org.uk> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Vladimir Serbinenko
parent
fb2a9a9e30
commit
26ca08caf8
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@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select H8_DOCK_EARLY_INIT
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select DRIVERS_LENOVO_WACOM
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select INTEL_EDID
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config MAINBOARD_DIR
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string
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@ -20,6 +20,3 @@
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smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c
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romstage-y += dock.c
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ramstage-y += dock.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915io.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c
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@ -22,6 +22,11 @@
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chip northbridge/intel/i945
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register "gpu_hotplug" = "0x00000220"
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register "gpu_lvds_use_spread_spectrum_clock" = "1"
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register "gpu_lvds_is_dual_channel" = "0"
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register "gpu_backlight" = "0x1280128"
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device cpu_cluster 0 on
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chip cpu/intel/socket_mFCPGA478
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device lapic 0 on end
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@ -1,239 +0,0 @@
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/*
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* Copyright 2013 Google Inc.
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* Copyright © 2008 Keith Packard
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that copyright
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* notice and this permission notice appear in supporting documentation, and
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* that the name of the copyright holders not be used in advertising or
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* publicity pertaining to distribution of the software without specific,
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* written prior permission. The copyright holders make no representations
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* about the suitability of this software for any purpose. It is provided "as
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* is" without express or implied warranty.
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*
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* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
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* OF THIS SOFTWARE.
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*/
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#ifndef _DRM_DP_HELPER_H_
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#define _DRM_DP_HELPER_H_
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/* From the VESA DisplayPort spec */
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#define AUX_NATIVE_WRITE 0x8
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#define AUX_NATIVE_READ 0x9
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#define AUX_I2C_WRITE 0x0
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#define AUX_I2C_READ 0x1
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#define AUX_I2C_STATUS 0x2
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#define AUX_I2C_MOT 0x4
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#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
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#define AUX_NATIVE_REPLY_NACK (0x1 << 4)
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#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
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#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
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#define AUX_I2C_REPLY_ACK (0x0 << 6)
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#define AUX_I2C_REPLY_NACK (0x1 << 6)
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#define AUX_I2C_REPLY_DEFER (0x2 << 6)
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#define AUX_I2C_REPLY_MASK (0x3 << 6)
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/* AUX CH addresses */
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/* DPCD */
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#define DP_DPCD_REV 0x000
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#define DP_MAX_LINK_RATE 0x001
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#define DP_MAX_LANE_COUNT 0x002
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# define DP_MAX_LANE_COUNT_MASK 0x1f
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# define DP_TPS3_SUPPORTED (1 << 6)
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# define DP_ENHANCED_FRAME_CAP (1 << 7)
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#define DP_MAX_DOWNSPREAD 0x003
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# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
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#define DP_NORP 0x004
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#define DP_DOWNSTREAMPORT_PRESENT 0x005
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# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
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# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
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/* 00b = DisplayPort */
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/* 01b = Analog */
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/* 10b = TMDS or HDMI */
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/* 11b = Other */
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# define DP_FORMAT_CONVERSION (1 << 3)
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#define DP_MAIN_LINK_CHANNEL_CODING 0x006
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#define DP_EDP_CONFIGURATION_CAP 0x00d
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#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
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#define DP_PSR_SUPPORT 0x070
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# define DP_PSR_IS_SUPPORTED 1
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#define DP_PSR_CAPS 0x071
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# define DP_PSR_NO_TRAIN_ON_EXIT 1
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# define DP_PSR_SETUP_TIME_330 (0 << 1)
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# define DP_PSR_SETUP_TIME_275 (1 << 1)
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# define DP_PSR_SETUP_TIME_220 (2 << 1)
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# define DP_PSR_SETUP_TIME_165 (3 << 1)
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# define DP_PSR_SETUP_TIME_110 (4 << 1)
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# define DP_PSR_SETUP_TIME_55 (5 << 1)
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# define DP_PSR_SETUP_TIME_0 (6 << 1)
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# define DP_PSR_SETUP_TIME_MASK (7 << 1)
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# define DP_PSR_SETUP_TIME_SHIFT 1
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/* link configuration */
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#define DP_LINK_BW_SET 0x100
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# define DP_LINK_BW_1_62 0x06
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# define DP_LINK_BW_2_7 0x0a
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# define DP_LINK_BW_5_4 0x14
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#define DP_LANE_COUNT_SET 0x101
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# define DP_LANE_COUNT_MASK 0x0f
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# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
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#define DP_TRAINING_PATTERN_SET 0x102
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# define DP_TRAINING_PATTERN_DISABLE 0
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# define DP_TRAINING_PATTERN_1 1
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# define DP_TRAINING_PATTERN_2 2
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# define DP_TRAINING_PATTERN_3 3
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# define DP_TRAINING_PATTERN_MASK 0x3
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# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
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# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
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# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
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# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
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# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
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# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
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# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
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# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
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# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
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# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
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# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
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#define DP_TRAINING_LANE0_SET 0x103
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#define DP_TRAINING_LANE1_SET 0x104
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#define DP_TRAINING_LANE2_SET 0x105
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#define DP_TRAINING_LANE3_SET 0x106
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# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
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# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
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# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
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# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
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# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
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# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
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#define DP_DOWNSPREAD_CTRL 0x107
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# define DP_SPREAD_AMP_0_5 (1 << 4)
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#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
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# define DP_SET_ANSI_8B10B (1 << 0)
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#define DP_PSR_EN_CFG 0x170
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# define DP_PSR_ENABLE (1 << 0)
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# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
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# define DP_PSR_CRC_VERIFICATION (1 << 2)
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# define DP_PSR_FRAME_CAPTURE (1 << 3)
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#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
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# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
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# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
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# define DP_CP_IRQ (1 << 2)
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# define DP_SINK_SPECIFIC_IRQ (1 << 6)
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#define DP_EDP_CONFIGURATION_SET 0x10a
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#define DP_LANE0_1_STATUS 0x202
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#define DP_LANE2_3_STATUS 0x203
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# define DP_LANE_CR_DONE (1 << 0)
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# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
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# define DP_LANE_SYMBOL_LOCKED (1 << 2)
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#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
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DP_LANE_CHANNEL_EQ_DONE | \
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DP_LANE_SYMBOL_LOCKED)
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#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
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#define DP_INTERLANE_ALIGN_DONE (1 << 0)
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#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
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#define DP_LINK_STATUS_UPDATED (1 << 7)
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#define DP_SINK_STATUS 0x205
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#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
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#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
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#define DP_ADJUST_REQUEST_LANE0_1 0x206
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#define DP_ADJUST_REQUEST_LANE2_3 0x207
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# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
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# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
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# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
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# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
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# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
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# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
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# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
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# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
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#define DP_TEST_REQUEST 0x218
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# define DP_TEST_LINK_TRAINING (1 << 0)
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# define DP_TEST_LINK_PATTERN (1 << 1)
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# define DP_TEST_LINK_EDID_READ (1 << 2)
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# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
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#define DP_TEST_LINK_RATE 0x219
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# define DP_LINK_RATE_162 (0x6)
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# define DP_LINK_RATE_27 (0xa)
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#define DP_TEST_LANE_COUNT 0x220
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#define DP_TEST_PATTERN 0x221
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#define DP_TEST_RESPONSE 0x260
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# define DP_TEST_ACK (1 << 0)
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# define DP_TEST_NAK (1 << 1)
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# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
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#define DP_SET_POWER 0x600
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# define DP_SET_POWER_D0 0x1
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# define DP_SET_POWER_D3 0x2
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#define DP_PSR_ERROR_STATUS 0x2006
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# define DP_PSR_LINK_CRC_ERROR (1 << 0)
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# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
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#define DP_PSR_ESI 0x2007
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# define DP_PSR_CAPS_CHANGE (1 << 0)
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#define DP_PSR_STATUS 0x2008
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# define DP_PSR_SINK_INACTIVE 0
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# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
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# define DP_PSR_SINK_ACTIVE_RFB 2
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# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
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# define DP_PSR_SINK_ACTIVE_RESYNC 4
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# define DP_PSR_SINK_INTERNAL_ERROR 7
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# define DP_PSR_SINK_STATE_MASK 0x07
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#define MODE_I2C_START 1
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#define MODE_I2C_WRITE 2
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#define MODE_I2C_READ 4
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#define MODE_I2C_STOP 8
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#endif /* _DRM_DP_HELPER_H_ */
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@ -1,373 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <string.h>
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#include <stdlib.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <delay.h>
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#include <pc80/mc146818rtc.h>
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <arch/interrupt.h>
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#include <boot/coreboot_tables.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <smbios.h>
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#include <device/pci.h>
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#include <ec/google/chromeec/ec.h>
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#include <cbfs_core.h>
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#include <cpu/x86/tsc.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <edid.h>
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#include "i915io.h"
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enum {
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vmsg = 1, vio = 2, vspin = 4,
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};
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#define PGETLB_CTL 0x2020
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static int verbose = 0;
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static unsigned int *mmio;
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static unsigned int graphics;
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static unsigned short addrport;
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static unsigned short dataport;
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static unsigned int physbase;
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#define PGETBL_CTL 0x2020
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#define PGETBL_ENABLED 0x00000001
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static u32 htotal, hblank, hsync, vtotal, vblank, vsync;
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const u8 x60_edid_data[] = {
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0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x30, 0xae, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x0f, 0x01, 0x03, 0x80, 0x19, 0x12, 0x78, 0xea, 0xed, 0x75, 0x91, 0x57, 0x4f, 0x8b, 0x26,
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0x21, 0x50, 0x54, 0x21, 0x08, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
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0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x28, 0x15, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30, 0x18, 0x88,
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0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0xed, 0x10, 0x00, 0x40, 0x41, 0x00, 0x26, 0x30,
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0x18, 0x88, 0x36, 0x00, 0xf6, 0xb9, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x61,
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0x43, 0x32, 0x61, 0x43, 0x28, 0x0f, 0x01, 0x00, 0x4c, 0xa3, 0x58, 0x4a, 0x00, 0x00, 0x00, 0xfe,
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0x00, 0x4c, 0x54, 0x4e, 0x31, 0x32, 0x31, 0x58, 0x4a, 0x2d, 0x4c, 0x30, 0x37, 0x0a, 0x00, 0x00,
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};
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#define READ32(addr) io_i915_READ32(addr)
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#define WRITE32(val, addr) io_i915_WRITE32(val, addr)
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static char *regname(unsigned long addr)
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{
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static char name[16];
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snprintf(name, sizeof (name), "0x%lx", addr);
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return name;
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}
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unsigned long io_i915_READ32(unsigned long addr)
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{
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unsigned long val;
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outl(addr, addrport);
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val = inl(dataport);
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if (verbose & vio)
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printk(BIOS_SPEW, "%s: Got %08lx\n", regname(addr), val);
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return val;
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}
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void io_i915_WRITE32(unsigned long val, unsigned long addr)
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{
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if (verbose & vio)
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printk(BIOS_SPEW, "%s: outl %08lx\n", regname(addr), val);
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outl(addr, addrport);
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outl(val, dataport);
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}
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/*
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2560
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4 words per
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4 *p
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10240
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4k bytes per page
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4096/p
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2.50
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1700 lines
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1700 * p
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4250.00
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PTEs
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||||
*/
|
||||
static void
|
||||
setgtt(int start, int end, unsigned long base, int inc)
|
||||
{
|
||||
int i;
|
||||
|
||||
printk(BIOS_INFO, "%s(%d,%d,0x%08lx,%d);\n",
|
||||
__func__, start, end, base, inc);
|
||||
|
||||
for (i = start; i < end; i++) {
|
||||
u32 word = base + i*inc;
|
||||
WRITE32(word|1, (i*4)|1);
|
||||
}
|
||||
}
|
||||
|
||||
int gtt_setup(unsigned int mmiobase);
|
||||
int gtt_setup(unsigned int mmiobase)
|
||||
{
|
||||
unsigned long PGETBL_save;
|
||||
|
||||
PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED;
|
||||
PGETBL_save |= PGETBL_ENABLED;
|
||||
|
||||
PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), BSM) & 0xfffff000;
|
||||
PGETBL_save |= 2; /* set GTT to 256kb */
|
||||
|
||||
write32(mmiobase + GFX_FLSH_CNTL, 0);
|
||||
|
||||
write32(mmiobase + PGETBL_CTL, PGETBL_save);
|
||||
|
||||
/* verify */
|
||||
if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) {
|
||||
printk(BIOS_DEBUG, "gtt_setup is enabled.\n");
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "gtt_setup failed!!!\n");
|
||||
return 1;
|
||||
}
|
||||
write32(mmiobase + GFX_FLSH_CNTL, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static unsigned long tickspermicrosecond = 1795;
|
||||
static unsigned long long globalstart;
|
||||
|
||||
static unsigned long
|
||||
microseconds(unsigned long long start, unsigned long long end)
|
||||
{
|
||||
unsigned long ret;
|
||||
ret = ((end - start)/tickspermicrosecond);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static unsigned long globalmicroseconds(void)
|
||||
{
|
||||
return microseconds(globalstart, rdtscll());
|
||||
}
|
||||
|
||||
extern struct iodef iodefs[];
|
||||
extern int niodefs;
|
||||
|
||||
/* fill the palette. This runs when the P opcode is hit. */
|
||||
static void palette(void)
|
||||
{
|
||||
int i;
|
||||
unsigned long color = 0;
|
||||
|
||||
for (i = 0; i < 256; i++, color += 0x010101)
|
||||
io_i915_WRITE32(color, _LGC_PALETTE_A + (i<<2));
|
||||
}
|
||||
|
||||
static unsigned long times[4096];
|
||||
|
||||
static int run(int index)
|
||||
{
|
||||
int i, prev = 0;
|
||||
struct iodef *id, *lastidread = 0;
|
||||
unsigned long u, t;
|
||||
if (index >= niodefs)
|
||||
return index;
|
||||
/* state machine! */
|
||||
for (i = index, id = &iodefs[i]; id->op; i++, id++) {
|
||||
switch (id->op) {
|
||||
case M:
|
||||
if (verbose & vmsg)
|
||||
printk(BIOS_SPEW, "%ld: %s\n",
|
||||
globalmicroseconds(), id->msg);
|
||||
break;
|
||||
case P:
|
||||
palette();
|
||||
break;
|
||||
case R:
|
||||
u = READ32(id->addr);
|
||||
if (verbose & vio)
|
||||
printk(BIOS_SPEW, "\texpect %08lx\n", id->data);
|
||||
/* we're looking for something. */
|
||||
if (lastidread->addr == id->addr) {
|
||||
/* they're going to be polling.
|
||||
* just do it 1000 times
|
||||
*/
|
||||
for (t = 0; t < 1000 && id->data != u; t++)
|
||||
u = READ32(id->addr);
|
||||
|
||||
if (verbose & vspin)
|
||||
printk(BIOS_SPEW,
|
||||
"%s: # loops %ld got %08lx want %08lx\n",
|
||||
regname(id->addr),
|
||||
t, u, id->data);
|
||||
}
|
||||
lastidread = id;
|
||||
break;
|
||||
case W:
|
||||
WRITE32(id->data, id->addr);
|
||||
if (id->addr == PCH_PP_CONTROL) {
|
||||
if (verbose & vio)
|
||||
printk(BIOS_SPEW, "PCH_PP_CONTROL\n");
|
||||
switch (id->data & 0xf) {
|
||||
case 8:
|
||||
break;
|
||||
case 7:
|
||||
break;
|
||||
default:
|
||||
udelay(100000);
|
||||
if (verbose & vio)
|
||||
printk(BIOS_SPEW, "U %d\n",
|
||||
100000);
|
||||
}
|
||||
}
|
||||
break;
|
||||
case V:
|
||||
if (id->count < 8) {
|
||||
prev = verbose;
|
||||
verbose = id->count;
|
||||
} else {
|
||||
verbose = prev;
|
||||
}
|
||||
printk(BIOS_SPEW, "Change verbosity to %d\n", verbose);
|
||||
break;
|
||||
case I:
|
||||
printk(BIOS_SPEW, "run: return %d\n", i+1);
|
||||
return i+1;
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_SPEW, "BAD TABLE, opcode %d @ %d\n",
|
||||
id->op, i);
|
||||
return -1;
|
||||
}
|
||||
if (id->udelay)
|
||||
udelay(id->udelay);
|
||||
if (i < ARRAY_SIZE(times))
|
||||
times[i] = globalmicroseconds();
|
||||
}
|
||||
printk(BIOS_SPEW, "run: return %d\n", i);
|
||||
return i+1;
|
||||
}
|
||||
|
||||
int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
|
||||
unsigned int gfx);
|
||||
|
||||
int i915lightup(unsigned int pphysbase, unsigned int piobase,
|
||||
unsigned int pmmio, unsigned int pgfx)
|
||||
{
|
||||
static struct edid edid;
|
||||
|
||||
int index;
|
||||
unsigned long temp;
|
||||
mmio = (void *)pmmio;
|
||||
addrport = piobase;
|
||||
dataport = addrport + 4;
|
||||
physbase = pphysbase;
|
||||
graphics = pgfx;
|
||||
printk(BIOS_SPEW,
|
||||
"i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n",
|
||||
(void *)graphics, mmio, addrport, physbase);
|
||||
globalstart = rdtscll();
|
||||
|
||||
|
||||
decode_edid((unsigned char *)&x60_edid_data,
|
||||
sizeof(x60_edid_data), &edid);
|
||||
|
||||
htotal = (edid.ha - 1) | ((edid.ha + edid.hbl - 1) << 16);
|
||||
printk(BIOS_SPEW, "I915_WRITE(HTOTAL(pipe), %08x)\n", htotal);
|
||||
|
||||
hblank = (edid.ha - 1) | ((edid.ha + edid.hbl - 1) << 16);
|
||||
printk(BIOS_SPEW, "I915_WRITE(HBLANK(pipe),0x%08x)\n", hblank);
|
||||
|
||||
hsync = (edid.ha + edid.hso - 1) |
|
||||
((edid.ha + edid.hso + edid.hspw - 1) << 16);
|
||||
printk(BIOS_SPEW, "I915_WRITE(HSYNC(pipe),0x%08x)\n", hsync);
|
||||
|
||||
vtotal = (edid.va - 1) | ((edid.va + edid.vbl - 1) << 16);
|
||||
printk(BIOS_SPEW, "I915_WRITE(VTOTAL(pipe), %08x)\n", vtotal);
|
||||
|
||||
vblank = (edid.va - 1) | ((edid.va + edid.vbl - 1) << 16);
|
||||
printk(BIOS_SPEW, "I915_WRITE(VBLANK(pipe),0x%08x)\n", vblank);
|
||||
|
||||
vsync = (edid.va + edid.vso - 1) |
|
||||
((edid.va + edid.vso + edid.vspw - 1) << 16);
|
||||
printk(BIOS_SPEW, "I915_WRITE(VSYNC(pipe),0x%08x)\n", vsync);
|
||||
|
||||
printk(BIOS_SPEW, "Table has %d elements\n", niodefs);
|
||||
|
||||
index = run(0);
|
||||
printk(BIOS_SPEW, "Run returns %d\n", index);
|
||||
|
||||
verbose = 0;
|
||||
/* GTT is the Global Translation Table for the graphics pipeline.
|
||||
* It is used to translate graphics addresses to physical
|
||||
* memory addresses. As in the CPU, GTTs map 4K pages.
|
||||
* There are 32 bits per pixel, or 4 bytes,
|
||||
* which means 1024 pixels per page.
|
||||
* There are 4250 GTTs on Link:
|
||||
* 2650 (X) * 1700 (Y) pixels / 1024 pixels per page.
|
||||
* The setgtt function adds a further bit of flexibility:
|
||||
* it allows you to set a range (the first two parameters) to point
|
||||
* to a physical address (third parameter);the physical address is
|
||||
* incremented by a count (fourth parameter) for each GTT in the
|
||||
* range.
|
||||
* Why do it this way? For ultrafast startup,
|
||||
* we can point all the GTT entries to point to one page,
|
||||
* and set that page to 0s:
|
||||
* memset(physbase, 0, 4096);
|
||||
* setgtt(0, 4250, physbase, 0);
|
||||
* this takes about 2 ms, and is a win because zeroing
|
||||
* the page takes a up to 200 ms. We will be exploiting this
|
||||
* trick in a later rev of this code.
|
||||
* This call sets the GTT to point to a linear range of pages
|
||||
* starting at physbase.
|
||||
*/
|
||||
|
||||
if (gtt_setup(pmmio)) {
|
||||
printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
setgtt(0, 800 , physbase, 4096);
|
||||
|
||||
temp = READ32(PGETLB_CTL);
|
||||
printk(BIOS_INFO, "GTT PGETLB_CTL register: 0x%lx\n", temp);
|
||||
|
||||
if (temp & 1)
|
||||
printk(BIOS_INFO, "GTT Enabled\n");
|
||||
else
|
||||
printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n");
|
||||
|
||||
printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n",
|
||||
(void *)graphics, FRAME_BUFFER_BYTES);
|
||||
memset((void *)graphics, 0x00, FRAME_BUFFER_BYTES);
|
||||
|
||||
printk(BIOS_SPEW, "%ld microseconds\n", globalmicroseconds());
|
||||
|
||||
set_vbe_mode_info_valid(&edid, graphics);
|
||||
|
||||
return 1;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,86 +0,0 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2012 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include "i915_reg.h"
|
||||
#include "drm_dp_helper.h"
|
||||
|
||||
/* things that are, strangely, not defined anywhere? */
|
||||
#define PCH_PP_UNLOCK 0xabcd0000
|
||||
#define WMx_LP_SR_EN (1<<31)
|
||||
|
||||
/* Google Link-specific defines */
|
||||
/* how many 4096-byte pages do we need for the framebuffer?
|
||||
* There are 32 bits per pixel, or 4 bytes,
|
||||
* which means 1024 pixels per page.
|
||||
* HencetThere are 4250 GTTs on Link:
|
||||
* 1024 (X) * 768 (Y) pixels / 1024 pixels per page.
|
||||
*/
|
||||
#define FRAME_BUFFER_PAGES ((1024*768)/1024)
|
||||
#define FRAME_BUFFER_BYTES (0x300000)
|
||||
|
||||
/* One-letter commands for code not meant to be ready for humans.
|
||||
* The code was generated by a set of programs/scripts.
|
||||
* M print out a kernel message
|
||||
* R read a register. We do these mainly to ensure that if hardware wanted
|
||||
* the register read, it was read; also, in debug, we can see what was expected
|
||||
* and what was found. This has proven *very* useful to get this debugged.
|
||||
* The udelay, if non-zero, will make sure there is a
|
||||
* udelay() call with the value.
|
||||
* The count is from the kernel and tells us how many times this read was done.
|
||||
* Also useful for debugging and the state
|
||||
* machine uses the info to drive a poll.
|
||||
* W Write a register
|
||||
* V set verbosity. It's a bit mask.
|
||||
* 0 -> nothing
|
||||
* 1 -> print kernel messages
|
||||
* 2 -> print IO ops
|
||||
* 4 -> print the number of times we spin on a register in a poll
|
||||
* 8 -> restore whatever the previous verbosity level was
|
||||
* (only one deep stack)
|
||||
*
|
||||
* Again, this is not really meant for human consumption. There is not a poll
|
||||
* operator as such because, sometimes, there is a read/write/read where the
|
||||
* second read is a poll, and this chipset is so touchy I'm reluctant to move
|
||||
* things around and/or delete too many reads.
|
||||
*/
|
||||
#define M 1
|
||||
#define R 2
|
||||
#define W 4
|
||||
#define V 8
|
||||
#define I 16
|
||||
#define P 32
|
||||
|
||||
struct iodef {
|
||||
unsigned char op;
|
||||
unsigned int count;
|
||||
const char *msg;
|
||||
unsigned long addr;
|
||||
unsigned long data;
|
||||
unsigned long udelay;
|
||||
};
|
||||
|
||||
/* i915.c */
|
||||
unsigned long io_i915_READ32(unsigned long addr);
|
||||
void io_i915_WRITE32(unsigned long val, unsigned long addr);
|
||||
|
||||
/* intel_dp.c */
|
||||
u32 pack_aux(u32 *src, int src_bytes);
|
||||
void unpack_aux(u32 src, u32 *dst, int dst_bytes);
|
||||
int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
|
||||
u32 *recv, int recv_size);
|
||||
|
|
@ -1,167 +0,0 @@
|
|||
/*
|
||||
* Copyright 2013 Google Inc.
|
||||
* Copyright © 2008 Intel Corporation
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the next
|
||||
* paragraph) shall be included in all copies or substantial portions of the
|
||||
* Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
|
||||
* IN THE SOFTWARE.
|
||||
*
|
||||
* Authors:
|
||||
* Keith Packard <keithp@keithp.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <stdint.h>
|
||||
#include <delay.h>
|
||||
#include "i915io.h"
|
||||
|
||||
u32
|
||||
pack_aux(u32 *src32, int src_bytes)
|
||||
{
|
||||
u8 *src = (u8 *)src32;
|
||||
int i;
|
||||
u32 v = 0;
|
||||
|
||||
if (src_bytes > 4)
|
||||
src_bytes = 4;
|
||||
for (i = 0; i < src_bytes; i++)
|
||||
v |= ((u32) src[i]) << ((3-i) * 8);
|
||||
return v;
|
||||
}
|
||||
|
||||
void
|
||||
unpack_aux(u32 src, u32 *dst32, int dst_bytes)
|
||||
{
|
||||
u8 *dst = (u8 *)dst32;
|
||||
|
||||
int i;
|
||||
if (dst_bytes > 4)
|
||||
dst_bytes = 4;
|
||||
for (i = 0; i < dst_bytes; i++)
|
||||
dst[i] = src >> ((3-i) * 8);
|
||||
}
|
||||
|
||||
int
|
||||
intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
|
||||
u32 *recv, int recv_size)
|
||||
{
|
||||
int i;
|
||||
int recv_bytes;
|
||||
u32 status;
|
||||
u32 aux_clock_divider;
|
||||
int try, precharge = 5;
|
||||
|
||||
/* The clock divider is based off the hrawclk,
|
||||
* and would like to run at 2MHz. So, take the
|
||||
* hrawclk value and divide by 2 and use that
|
||||
*
|
||||
* Note that PCH attached eDP panels should use a 125MHz input
|
||||
* clock divider.
|
||||
*/
|
||||
/* 200 on link */
|
||||
aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
|
||||
|
||||
/* Try to wait for any previous AUX channel activity */
|
||||
for (try = 0; try < 3; try++) {
|
||||
status = io_i915_READ32(ch_ctl);
|
||||
if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
|
||||
break;
|
||||
udelay(1000);
|
||||
}
|
||||
|
||||
if (try == 3) {
|
||||
printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
|
||||
printk(BIOS_SPEW, "dp_aux_ch not started status 0x%08lx\n",
|
||||
io_i915_READ32(ch_ctl));
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Must try at least 3 times according to DP spec */
|
||||
for (try = 0; try < 5; try++) {
|
||||
/* Load the send data into the aux channel data registers */
|
||||
for (i = 0; i < send_bytes; i += 4)
|
||||
io_i915_WRITE32(send[i], ch_data + i);
|
||||
|
||||
/* Send the command and wait for it to complete */
|
||||
io_i915_WRITE32(
|
||||
DP_AUX_CH_CTL_SEND_BUSY |
|
||||
DP_AUX_CH_CTL_TIME_OUT_400us |
|
||||
(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
|
||||
(precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
|
||||
(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
|
||||
DP_AUX_CH_CTL_DONE |
|
||||
DP_AUX_CH_CTL_TIME_OUT_ERROR |
|
||||
DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl);
|
||||
for (;;) {
|
||||
status = io_i915_READ32(ch_ctl);
|
||||
if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
|
||||
break;
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
/* Clear done status and any errors */
|
||||
io_i915_WRITE32(
|
||||
status |
|
||||
DP_AUX_CH_CTL_DONE |
|
||||
DP_AUX_CH_CTL_TIME_OUT_ERROR |
|
||||
DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl);
|
||||
|
||||
if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
|
||||
DP_AUX_CH_CTL_RECEIVE_ERROR))
|
||||
continue;
|
||||
if (status & DP_AUX_CH_CTL_DONE)
|
||||
break;
|
||||
}
|
||||
|
||||
if ((status & DP_AUX_CH_CTL_DONE) == 0) {
|
||||
printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
|
||||
printk(BIOS_SPEW, "dp_aux_ch not done status 0x%08x\n", status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Check for timeout or receive error.
|
||||
* Timeouts occur when the sink is not connected
|
||||
*/
|
||||
if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
|
||||
printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
|
||||
printk(BIOS_SPEW,
|
||||
"dp_aux_ch receive error status 0x%08x\n", status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Timeouts occur when the device isn't connected, so they're
|
||||
* "normal" -- don't fill the kernel log with these */
|
||||
if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
|
||||
printk(BIOS_SPEW, "[000000.0] [drm:%s], ", __func__);
|
||||
printk(BIOS_SPEW, "dp_aux_ch timeout status 0x%08x\n", status);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Unload any bytes sent back from the other side */
|
||||
recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
|
||||
DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
|
||||
if (recv_bytes > recv_size)
|
||||
recv_bytes = recv_size;
|
||||
|
||||
for (i = 0; i < recv_bytes; i += 4)
|
||||
unpack_aux(io_i915_READ32(ch_data + i),
|
||||
recv + i, recv_bytes - i);
|
||||
|
||||
return recv_bytes;
|
||||
}
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
struct northbridge_intel_i945_config {
|
||||
u32 gpu_hotplug;
|
||||
u32 gpu_backlight;
|
||||
int gpu_lvds_use_spread_spectrum_clock;
|
||||
int gpu_lvds_is_dual_channel;
|
||||
};
|
||||
|
|
@ -24,10 +24,360 @@
|
|||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <edid.h>
|
||||
#include <drivers/intel/gma/edid.h>
|
||||
#include <drivers/intel/gma/i915.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "i945.h"
|
||||
#include "chip.h"
|
||||
|
||||
#define GDRST 0xc0
|
||||
|
||||
#define LVDS_CLOCK_A_POWERUP_ALL (3 << 8)
|
||||
#define LVDS_CLOCK_B_POWERUP_ALL (3 << 4)
|
||||
#define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2)
|
||||
#define DISPPLANE_BGRX888 (0x6<<26)
|
||||
#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
|
||||
|
||||
#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
|
||||
|
||||
#define PGETBL_CTL 0x2020
|
||||
#define PGETBL_ENABLED 0x00000001
|
||||
|
||||
#define BASE_FREQUENCY 120000
|
||||
|
||||
#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
|
||||
|
||||
static int gtt_setup(unsigned int mmiobase)
|
||||
{
|
||||
unsigned long PGETBL_save;
|
||||
|
||||
PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED;
|
||||
PGETBL_save |= PGETBL_ENABLED;
|
||||
|
||||
PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000;
|
||||
PGETBL_save |= 2; /* set GTT to 256kb */
|
||||
|
||||
write32(mmiobase + GFX_FLSH_CNTL, 0);
|
||||
|
||||
write32(mmiobase + PGETBL_CTL, PGETBL_save);
|
||||
|
||||
/* verify */
|
||||
if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) {
|
||||
printk(BIOS_DEBUG, "gtt_setup is enabled.\n");
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "gtt_setup failed!!!\n");
|
||||
return 1;
|
||||
}
|
||||
write32(mmiobase + GFX_FLSH_CNTL, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int intel_gma_init(struct northbridge_intel_i945_config *conf,
|
||||
unsigned int pphysbase, unsigned int piobase,
|
||||
unsigned int pmmio, unsigned int pgfx)
|
||||
{
|
||||
struct edid edid;
|
||||
u8 edid_data[128];
|
||||
unsigned long temp;
|
||||
int hpolarity, vpolarity;
|
||||
u32 candp1, candn;
|
||||
u32 best_delta = 0xffffffff;
|
||||
u32 target_frequency;
|
||||
u32 pixel_p1 = 1;
|
||||
u32 pixel_n = 1;
|
||||
u32 pixel_m1 = 1;
|
||||
u32 pixel_m2 = 1;
|
||||
u32 hactive, vactive, right_border, bottom_border;
|
||||
u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch;
|
||||
u32 i, j;
|
||||
u32 uma_size;
|
||||
u16 reg16;
|
||||
|
||||
pphysbase += 0x20000;
|
||||
|
||||
printk(BIOS_SPEW,
|
||||
"i915lightup: graphics %p mmio %08x addrport %04x physbase %08x\n",
|
||||
(void *)pgfx, pmmio, piobase, pphysbase);
|
||||
|
||||
intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data, 128);
|
||||
decode_edid(edid_data, sizeof(edid_data), &edid);
|
||||
|
||||
hpolarity = (edid.phsync == '-');
|
||||
vpolarity = (edid.pvsync == '-');
|
||||
hactive = edid.x_resolution;
|
||||
vactive = edid.y_resolution;
|
||||
right_border = edid.hborder;
|
||||
bottom_border = edid.vborder;
|
||||
vblank = edid.vbl;
|
||||
hblank = edid.hbl;
|
||||
vsync = edid.vspw;
|
||||
hsync = edid.hspw;
|
||||
hfront_porch = edid.hso;
|
||||
vfront_porch = edid.vso;
|
||||
|
||||
for (i = 0; i < 2; i++)
|
||||
for (j = 0; j < 0x100; j++)
|
||||
/* R=j, G=j, B=j. */
|
||||
write32(pmmio + PALETTE(i) + 4 * j, 0x10101 * j);
|
||||
|
||||
write32(pmmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
|
||||
| (read32(pmmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
|
||||
|
||||
write32(pmmio + MI_ARB_STATE, MI_ARB_C3_LP_WRITE_ENABLE | (1 << 27));
|
||||
/* Clean registers. */
|
||||
for (i = 0; i < 0x20; i += 4)
|
||||
write32(pmmio + RENDER_RING_BASE + i, 0);
|
||||
for (i = 0; i < 0x20; i += 4)
|
||||
write32(pmmio + FENCE_REG_965_0 + i, 0);
|
||||
write32(pmmio + PP_ON_DELAYS, 0);
|
||||
write32(pmmio + PP_OFF_DELAYS, 0);
|
||||
|
||||
/* Disable VGA. */
|
||||
write32(pmmio + VGACNTRL, VGA_DISP_DISABLE);
|
||||
|
||||
/* Disable pipes. */
|
||||
write32(pmmio + PIPECONF(0), 0);
|
||||
write32(pmmio + PIPECONF(1), 0);
|
||||
|
||||
/* Init PRB0. */
|
||||
write32(pmmio + HWS_PGA, 0x352d2000);
|
||||
write32(pmmio + PRB0_CTL, 0);
|
||||
write32(pmmio + PRB0_HEAD, 0);
|
||||
write32(pmmio + PRB0_TAIL, 0);
|
||||
write32(pmmio + PRB0_START, 0);
|
||||
write32(pmmio + PRB0_CTL, 0x0001f001);
|
||||
|
||||
write32(pmmio + D_STATE, DSTATE_PLL_D3_OFF
|
||||
| DSTATE_GFX_CLOCK_GATING | DSTATE_DOT_CLOCK_GATING);
|
||||
write32(pmmio + ECOSKPD, 0x00010000);
|
||||
write32(pmmio + HWSTAM, 0xeffe);
|
||||
write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug);
|
||||
write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS);
|
||||
|
||||
target_frequency = conf->gpu_lvds_is_dual_channel ? edid.pixel_clock
|
||||
: (2 * edid.pixel_clock);
|
||||
|
||||
/* Find suitable divisors. */
|
||||
for (candp1 = 1; candp1 <= 8; candp1++) {
|
||||
for (candn = 5; candn <= 10; candn++) {
|
||||
u32 cur_frequency;
|
||||
u32 m; /* 77 - 131. */
|
||||
u32 denom; /* 35 - 560. */
|
||||
u32 current_delta;
|
||||
|
||||
denom = candn * candp1 * 7;
|
||||
/* Doesnt overflow for up to
|
||||
5000000 kHz = 5 GHz. */
|
||||
m = (target_frequency * denom
|
||||
+ BASE_FREQUENCY / 2) / BASE_FREQUENCY;
|
||||
|
||||
if (m < 77 || m > 131)
|
||||
continue;
|
||||
|
||||
cur_frequency = (BASE_FREQUENCY * m) / denom;
|
||||
if (target_frequency > cur_frequency)
|
||||
current_delta = target_frequency - cur_frequency;
|
||||
else
|
||||
current_delta = cur_frequency - target_frequency;
|
||||
|
||||
if (best_delta > current_delta) {
|
||||
best_delta = current_delta;
|
||||
pixel_n = candn;
|
||||
pixel_p1 = candp1;
|
||||
pixel_m2 = ((m + 3) % 5) + 7;
|
||||
pixel_m1 = (m - pixel_m2) / 5;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (best_delta == 0xffffffff) {
|
||||
printk (BIOS_ERR, "Couldn't find GFX clock divisors\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
|
||||
hactive, vactive);
|
||||
printk(BIOS_DEBUG, "Borders %d x %d\n", right_border, bottom_border);
|
||||
printk(BIOS_DEBUG, "Blank %d x %d\n", hblank, vblank);
|
||||
printk(BIOS_DEBUG, "Sync %d x %d\n", hsync, vsync);
|
||||
printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch);
|
||||
printk(BIOS_DEBUG, (conf->gpu_lvds_use_spread_spectrum_clock
|
||||
? "Spread spectrum clock\n"
|
||||
: "DREF clock\n"));
|
||||
printk(BIOS_DEBUG, (conf->gpu_lvds_is_dual_channel
|
||||
? "Dual channel\n"
|
||||
: "Single channel\n"));
|
||||
printk(BIOS_DEBUG, "Polarities %d, %d\n",
|
||||
hpolarity, vpolarity);
|
||||
printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",
|
||||
pixel_n, pixel_m1, pixel_m2, pixel_p1);
|
||||
printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
|
||||
BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n
|
||||
/ (pixel_p1 * 7));
|
||||
|
||||
write32(pmmio + DSPCNTR(0), DISPPLANE_BGRX888
|
||||
| DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE);
|
||||
|
||||
mdelay(1);
|
||||
write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS
|
||||
| (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
|
||||
write32(pmmio + FP0(1),
|
||||
((pixel_n - 2) << 16)
|
||||
| ((pixel_m1 - 2) << 8) | pixel_m2);
|
||||
write32(pmmio + DPLL(1),
|
||||
DPLL_VGA_MODE_DIS |
|
||||
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
|
||||
| (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
|
||||
: DPLLB_LVDS_P2_CLOCK_DIV_14)
|
||||
| (conf->gpu_lvds_use_spread_spectrum_clock
|
||||
? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV
|
||||
: 0)
|
||||
| (pixel_p1 << 16)
|
||||
| (pixel_p1));
|
||||
mdelay(1);
|
||||
write32(pmmio + DPLL(1),
|
||||
DPLL_VGA_MODE_DIS |
|
||||
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
|
||||
| (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
|
||||
: DPLLB_LVDS_P2_CLOCK_DIV_14)
|
||||
| ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13)
|
||||
| (pixel_p1 << 16)
|
||||
| (pixel_p1));
|
||||
mdelay(1);
|
||||
write32(pmmio + HTOTAL(1),
|
||||
((hactive + right_border + hblank - 1) << 16)
|
||||
| (hactive - 1));
|
||||
write32(pmmio + HBLANK(1),
|
||||
((hactive + right_border + hblank - 1) << 16)
|
||||
| (hactive + right_border - 1));
|
||||
write32(pmmio + HSYNC(1),
|
||||
((hactive + right_border + hfront_porch + hsync - 1) << 16)
|
||||
| (hactive + right_border + hfront_porch - 1));
|
||||
|
||||
write32(pmmio + VTOTAL(1), ((vactive + bottom_border + vblank - 1) << 16)
|
||||
| (vactive - 1));
|
||||
write32(pmmio + VBLANK(1), ((vactive + bottom_border + vblank - 1) << 16)
|
||||
| (vactive + bottom_border - 1));
|
||||
write32(pmmio + VSYNC(1),
|
||||
(vactive + bottom_border + vfront_porch + vsync - 1)
|
||||
| (vactive + bottom_border + vfront_porch - 1));
|
||||
|
||||
write32(pmmio + PIPESRC(1), ((hactive - 1) << 16) | (vactive - 1));
|
||||
|
||||
/* Disable panel fitter (we're in native resolution). */
|
||||
write32(pmmio + PF_CTL(0), 0);
|
||||
write32(pmmio + PF_WIN_SZ(0), 0);
|
||||
write32(pmmio + PF_WIN_POS(0), 0);
|
||||
write32(pmmio + PFIT_PGM_RATIOS, 0);
|
||||
write32(pmmio + PFIT_CONTROL, 0);
|
||||
|
||||
mdelay(1);
|
||||
|
||||
write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16));
|
||||
write32(pmmio + DSPPOS(0), 0);
|
||||
|
||||
/* Backlight init. */
|
||||
write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK);
|
||||
write32(pmmio + FW_BLC, 0x011d011a);
|
||||
write32(pmmio + FW_BLC2, 0x00000102);
|
||||
write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK);
|
||||
write32(pmmio + FW_BLC_SELF, 0x0001003f);
|
||||
write32(pmmio + FW_BLC, 0x011d0109);
|
||||
write32(pmmio + FW_BLC2, 0x00000102);
|
||||
write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK);
|
||||
write32(pmmio + BLC_PWM_CTL, conf->gpu_backlight);
|
||||
|
||||
edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
|
||||
write32(pmmio + DSPADDR(0), 0);
|
||||
write32(pmmio + DSPSURF(0), 0);
|
||||
write32(pmmio + DSPSTRIDE(0), edid.bytes_per_line);
|
||||
write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888
|
||||
| DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE);
|
||||
mdelay(1);
|
||||
|
||||
write32(pmmio + PIPECONF(1), PIPECONF_ENABLE);
|
||||
write32(pmmio + LVDS, LVDS_ON
|
||||
| (hpolarity << 20) | (vpolarity << 21)
|
||||
| (conf->gpu_lvds_is_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
|
||||
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
|
||||
| LVDS_CLOCK_A_POWERUP_ALL
|
||||
| LVDS_PIPE(1));
|
||||
|
||||
write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
|
||||
write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
|
||||
mdelay(1);
|
||||
write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS
|
||||
| PANEL_POWER_ON | PANEL_POWER_RESET);
|
||||
|
||||
printk (BIOS_DEBUG, "waiting for panel powerup\n");
|
||||
while (1) {
|
||||
u32 reg32;
|
||||
reg32 = read32(pmmio + PP_STATUS);
|
||||
if ((reg32 & PP_SEQUENCE_MASK) == PP_SEQUENCE_NONE)
|
||||
break;
|
||||
}
|
||||
printk (BIOS_DEBUG, "panel powered up\n");
|
||||
|
||||
write32(pmmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
|
||||
|
||||
/* Clear interrupts. */
|
||||
write32(pmmio + DEIIR, 0xffffffff);
|
||||
write32(pmmio + SDEIIR, 0xffffffff);
|
||||
write32(pmmio + IIR, 0xffffffff);
|
||||
write32(pmmio + IMR, 0xffffffff);
|
||||
write32(pmmio + EIR, 0xffffffff);
|
||||
|
||||
if (gtt_setup(pmmio)) {
|
||||
printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Setup GTT. */
|
||||
|
||||
reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
|
||||
uma_size = 0;
|
||||
if (!(reg16 & 2)) {
|
||||
reg16 >>= 4;
|
||||
reg16 &= 7;
|
||||
switch (reg16) {
|
||||
case 1:
|
||||
uma_size = 1024;
|
||||
break;
|
||||
case 3:
|
||||
uma_size = 8192;
|
||||
break;
|
||||
}
|
||||
|
||||
printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
|
||||
}
|
||||
|
||||
for (i = 0; i < uma_size / 4; i++)
|
||||
{
|
||||
outl((i << 2) | 1, piobase);
|
||||
outl(pphysbase + (i << 12) + 1, piobase + 4);
|
||||
}
|
||||
|
||||
temp = read32(pmmio + PGETBL_CTL);
|
||||
printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp);
|
||||
|
||||
if (temp & 1)
|
||||
printk(BIOS_INFO, "GTT Enabled\n");
|
||||
else
|
||||
printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n");
|
||||
|
||||
printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n",
|
||||
(void *)pgfx, hactive * vactive * 4);
|
||||
memset((void *)pgfx, 0x00, hactive * vactive * 4);
|
||||
|
||||
set_vbe_mode_info_valid(&edid, pgfx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void gma_func0_init(struct device *dev)
|
||||
{
|
||||
u32 reg32;
|
||||
|
|
@ -41,8 +391,8 @@ static void gma_func0_init(struct device *dev)
|
|||
|
||||
/* IGD needs to be Bus Master */
|
||||
reg32 = pci_read_config32(dev, PCI_COMMAND);
|
||||
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
|
||||
|
||||
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER
|
||||
| PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
|
||||
|
||||
#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
|
||||
/* PCI Init, will run VBIOS */
|
||||
|
|
@ -54,22 +404,23 @@ static void gma_func0_init(struct device *dev)
|
|||
/* This should probably run before post VBIOS init. */
|
||||
printk(BIOS_SPEW, "Initializing VGA without OPROM.\n");
|
||||
u32 iobase, mmiobase, graphics_base;
|
||||
struct northbridge_intel_i945_config *conf = dev->chip_info;
|
||||
|
||||
iobase = dev->resource_list[1].base;
|
||||
mmiobase = dev->resource_list[0].base;
|
||||
graphics_base = dev->resource_list[2].base + 0x20000;
|
||||
graphics_base = dev->resource_list[2].base;
|
||||
|
||||
printk(BIOS_SPEW, "GMADR=0x%08x GTTADR=0x%08x\n",
|
||||
pci_read_config32(dev, GMADR),
|
||||
pci_read_config32(dev, GTTADR)
|
||||
);
|
||||
|
||||
int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx);
|
||||
u32 uma_memory_base = pci_read_config32(dev, BSM) & ~((1 << 20) - 1);
|
||||
int lightup_ok = i915lightup(uma_memory_base, iobase, mmiobase, graphics_base);
|
||||
if (lightup_ok)
|
||||
int err;
|
||||
err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf,
|
||||
iobase, mmiobase, graphics_base);
|
||||
if (err == 0)
|
||||
gfx_set_init_done(1);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/* This doesn't reclaim stolen UMA memory, but IGD could still
|
||||
|
|
@ -96,7 +447,7 @@ static void gma_func1_init(struct device *dev)
|
|||
/* IGD needs to be Bus Master, also enable IO accesss */
|
||||
reg32 = pci_read_config32(dev, PCI_COMMAND);
|
||||
pci_write_config32(dev, PCI_COMMAND, reg32 |
|
||||
PCI_COMMAND_MASTER | PCI_COMMAND_IO);
|
||||
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
|
||||
|
||||
if (get_option(&val, "tft_brightness") == CB_SUCCESS)
|
||||
pci_write_config8(dev, 0xf4, val);
|
||||
|
|
|
|||
Loading…
Reference in New Issue