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mb/google/brya/var/omnigul: Modify NVMe and UFS Storage support 

1. Add fw_config:STORAGE_UFS & STORAGE_NVME to switch storage.
2. rp11 off change to on.

BUG🅱️263846075
TEST=FW_NAME=omnigul emerge-brya coreboot

Change-Id: I35c02ac9cbb8442d7b4aae57f6c7b576b2b5f77b
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72090
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Jamie Chen 2023-01-19 16:42:07 +08:00 committed by Eric Lai
parent 74793855dd
commit 26d7303f01
1 changed files with 23 additions and 2 deletions
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25
src/mainboard/google/brya/variants/omnigul/overridetree.cb
View File

@ -1,3 +1,11 @@
fw_config
field STORAGE 2 3
option STORAGE_UNKNOWN 0
option STORAGE_UFS 1
option STORAGE_NVME 2
end
end
chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled"
@ -109,14 +117,27 @@ chip soc/intel/alderlake
end
end #I2C5
device ref pcie_rp8 off end
device ref pcie_rp9 off end
device ref pcie_rp11 on
register "pch_pcie_rp[PCH_RP(11)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
probe STORAGE STORAGE_UNKNOWN
probe STORAGE STORAGE_NVME
end
device ref ish on
chip drivers/intel/ish
register "add_acpi_dma_property" = "true"
device generic 0 on end
end
probe STORAGE STORAGE_UNKNOWN
probe STORAGE STORAGE_UFS
end
device ref ufs on
probe STORAGE STORAGE_UNKNOWN
probe STORAGE STORAGE_UFS
end
device ref ufs on end
device ref tbt_pcie_rp0 off end
device ref tbt_pcie_rp1 off end
device ref tbt_pcie_rp2 off end