soc/intel/cometlake: Use IntelFSP repo
Make use of the publicly-available FSP binaries and headers for Comet Lake. Also, remove the Comet Lake header files from src/vendorcode, since they are no longer necessary. Change-Id: I392cc7ee3bf5aa21753efd6eab4abd643b65ff94 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39372 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer
Patrick Georgi
parent
ba5062d78b
commit
26dc8f2c4e
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@ -56,7 +56,7 @@ config FSP_USE_REPO
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depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \
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SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \
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SOC_INTEL_ICELAKE || SOC_INTEL_WHISKEYLAKE || \
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SOC_INTEL_DENVERTON_NS
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SOC_INTEL_DENVERTON_NS || SOC_INTEL_COMETLAKE
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help
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When selecting this option, the SoC must set FSP_HEADER_PATH
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and FSP_FD_PATH correctly so FSP splitting works.
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@ -309,13 +309,14 @@ endchoice
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config FSP_HEADER_PATH
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string "Location of FSP headers"
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default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE
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default "src/vendorcode/intel/fsp/fsp2_0/cometlake/" if SOC_INTEL_COMETLAKE
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default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/Include/" if SOC_INTEL_COMETLAKE
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default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" if SOC_INTEL_CANNONLAKE
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config FSP_FD_PATH
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string
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depends on FSP_USE_REPO
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default "3rdparty/fsp/CoffeeLakeFspBinPkg/Fsp.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE
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default "3rdparty/fsp/CometLakeFspBinPkg/CometLake1/FSP.fd" if SOC_INTEL_COMETLAKE
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config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT
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int "Debug Consent for CNL"
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@ -1,68 +0,0 @@
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/** @file
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Header file for Firmware Version Information
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@copyright
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Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License which accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
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#define _FIRMWARE_VERSION_INFO_HOB_H_
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#include <Uefi/UefiMultiPhase.h>
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#include <Pi/PiBootMode.h>
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#include <Pi/PiHob.h>
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#pragma pack(1)
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///
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/// Firmware Version Structure
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///
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typedef struct {
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UINT8 MajorVersion;
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UINT8 MinorVersion;
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UINT8 Revision;
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UINT16 BuildNumber;
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} FIRMWARE_VERSION;
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///
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/// Firmware Version Information Structure
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///
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typedef struct {
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UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
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UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
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FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
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} FIRMWARE_VERSION_INFO;
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#ifndef __SMBIOS_STANDARD_H__
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///
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/// The Smbios structure header.
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///
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typedef struct {
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UINT8 Type;
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UINT8 Length;
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UINT16 Handle;
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} SMBIOS_STRUCTURE;
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#endif
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///
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/// Firmware Version Information HOB Structure
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///
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typedef struct {
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EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
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SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
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UINT8 Count; ///< Offset 28 Number of FVI elements included.
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///
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/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
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///
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} FIRMWARE_VERSION_INFO_HOB;
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#pragma pack()
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#endif // _FIRMWARE_VERSION_INFO_HOB_H_
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@ -1,48 +0,0 @@
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/** @file
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Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this
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list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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* Neither the name of Intel Corporation nor the names of its contributors may
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be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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THE POSSIBILITY OF SUCH DAMAGE.
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This file is automatically generated. Please do NOT modify !!!
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**/
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#ifndef __FSPUPD_H__
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#define __FSPUPD_H__
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#include <FspEas.h>
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#pragma pack(1)
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#define FSPT_UPD_SIGNATURE 0x545F4450554C4D43 /* 'CMLUPD_T' */
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#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4D43 /* 'CMLUPD_M' */
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#define FSPS_UPD_SIGNATURE 0x535F4450554C4D43 /* 'CMLUPD_S' */
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#pragma pack()
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#endif
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -1,186 +0,0 @@
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/** @file
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Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this
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list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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* Neither the name of Intel Corporation nor the names of its contributors may
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be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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THE POSSIBILITY OF SUCH DAMAGE.
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This file is automatically generated. Please do NOT modify !!!
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**/
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#ifndef __FSPTUPD_H__
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#define __FSPTUPD_H__
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#include <FspUpd.h>
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#pragma pack(1)
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/** Fsp T Core UPD
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**/
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typedef struct {
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/** Offset 0x0020
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**/
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UINT32 MicrocodeRegionBase;
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/** Offset 0x0024
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**/
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UINT32 MicrocodeRegionSize;
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/** Offset 0x0028
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**/
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UINT32 CodeRegionBase;
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/** Offset 0x002C
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**/
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UINT32 CodeRegionSize;
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/** Offset 0x0030
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**/
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UINT8 Reserved[16];
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} FSPT_CORE_UPD;
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/** Fsp T Configuration
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**/
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typedef struct {
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/** Offset 0x0040 - PcdSerialIoUartDebugEnable
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Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
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0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
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**/
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UINT8 PcdSerialIoUartDebugEnable;
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/** Offset 0x0041 - PcdSerialIoUartNumber - FSPT
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Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
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Core interface, it cannot be used for debug purpose.
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0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
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**/
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UINT8 PcdSerialIoUartNumber;
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/** Offset 0x0042 - PcdSerialIoUartMode - FSPT
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Select SerialIo Uart Controller mode
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0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
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4:SerialIoUartSkipInit
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**/
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UINT8 PcdSerialIoUartMode;
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/** Offset 0x0043
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**/
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UINT8 UnusedUpdSpace0;
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/** Offset 0x0044 - PcdSerialIoUartBaudRate - FSPT
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Set default BaudRate Supported from 0 - default to 6000000
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**/
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UINT32 PcdSerialIoUartBaudRate;
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/** Offset 0x0048 - Pci Express Base Address
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Base address to be programmed for Pci Express
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**/
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UINT64 PcdPciExpressBaseAddress;
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/** Offset 0x0050 - Pci Express Region Length
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Region Length to be programmed for Pci Express
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**/
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UINT32 PcdPciExpressRegionLength;
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/** Offset 0x0054 - PcdSerialIoUartParity - FSPT
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Set default Parity.
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0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
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**/
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UINT8 PcdSerialIoUartParity;
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/** Offset 0x0055 - PcdSerialIoUartDataBits - FSPT
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Set default word length. 0: Default, 5,6,7,8
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**/
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UINT8 PcdSerialIoUartDataBits;
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/** Offset 0x0056 - PcdSerialIoUartStopBits - FSPT
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Set default stop bits.
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0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
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**/
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UINT8 PcdSerialIoUartStopBits;
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/** Offset 0x0057 - PcdSerialIoUartAutoFlow - FSPT
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Enables UART hardware flow control, CTS and RTS lines.
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0: Disable, 1:Enable
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**/
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UINT8 PcdSerialIoUartAutoFlow;
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/** Offset 0x0058 - PcdSerialIoUartRxPinMux - FSPT
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Select RX pin muxing for SerialIo UART used for debug
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**/
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UINT32 PcdSerialIoUartRxPinMux;
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/** Offset 0x005C - PcdSerialIoUartTxPinMux - FSPT
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Select TX pin muxing for SerialIo UART used for debug
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**/
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UINT32 PcdSerialIoUartTxPinMux;
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/** Offset 0x0060 - PcdSerialIoUartRtsPinMux - FSPT
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Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
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for possible values.
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**/
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UINT32 PcdSerialIoUartRtsPinMux;
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/** Offset 0x0064 - PcdSerialIoUartCtsPinMux - FSPT
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Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
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for possible values.
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**/
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UINT32 PcdSerialIoUartCtsPinMux;
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/** Offset 0x0068
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**/
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UINT8 ReservedFsptUpd1[24];
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} FSP_T_CONFIG;
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/** Fsp T UPD Configuration
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**/
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typedef struct {
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/** Offset 0x0000
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**/
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FSP_UPD_HEADER FspUpdHeader;
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/** Offset 0x0020
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**/
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FSPT_CORE_UPD FsptCoreUpd;
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/** Offset 0x0040
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**/
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FSP_T_CONFIG FsptConfig;
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/** Offset 0x0080
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||||
**/
|
||||
UINT8 UnusedUpdSpace1[6];
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/** Offset 0x0086
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**/
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UINT16 UpdTerminator;
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} FSPT_UPD;
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#pragma pack()
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|
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#endif
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|
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@ -1,274 +0,0 @@
|
|||
/** @file
|
||||
This file contains definitions required for creation of
|
||||
Memory S3 Save data, Memory Info data and Memory Platform
|
||||
data hobs.
|
||||
|
||||
@copyright
|
||||
Copyright (c) 1999 - 2019, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
@par Specification Reference:
|
||||
**/
|
||||
#ifndef _MEM_INFO_HOB_H_
|
||||
#define _MEM_INFO_HOB_H_
|
||||
|
||||
#include <Uefi/UefiMultiPhase.h>
|
||||
#include <Pi/PiBootMode.h>
|
||||
#include <Pi/PiHob.h>
|
||||
|
||||
#pragma pack (push, 1)
|
||||
|
||||
extern EFI_GUID gSiMemoryS3DataGuid;
|
||||
extern EFI_GUID gSiMemoryInfoDataGuid;
|
||||
extern EFI_GUID gSiMemoryPlatformDataGuid;
|
||||
|
||||
#define MAX_NODE 1
|
||||
#define MAX_CH 2
|
||||
#define MAX_DIMM 2
|
||||
|
||||
///
|
||||
/// Host reset states from MRC.
|
||||
///
|
||||
#define WARM_BOOT 2
|
||||
|
||||
#define R_MC_CHNL_RANK_PRESENT 0x7C
|
||||
#define B_RANK0_PRS BIT0
|
||||
#define B_RANK1_PRS BIT1
|
||||
#define B_RANK2_PRS BIT4
|
||||
#define B_RANK3_PRS BIT5
|
||||
|
||||
///
|
||||
/// Defines taken from MRC so avoid having to include MrcInterface.h
|
||||
///
|
||||
|
||||
//
|
||||
// Matches MAX_SPD_SAVE define in MRC
|
||||
//
|
||||
#ifndef MAX_SPD_SAVE
|
||||
#define MAX_SPD_SAVE 29
|
||||
#endif
|
||||
|
||||
//
|
||||
// MRC version description.
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Major; ///< Major version number
|
||||
UINT8 Minor; ///< Minor version number
|
||||
UINT8 Rev; ///< Revision number
|
||||
UINT8 Build; ///< Build number
|
||||
} SiMrcVersion;
|
||||
|
||||
//
|
||||
// Matches MrcChannelSts enum in MRC
|
||||
//
|
||||
#ifndef CHANNEL_NOT_PRESENT
|
||||
#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
|
||||
#endif
|
||||
#ifndef CHANNEL_DISABLED
|
||||
#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
|
||||
#endif
|
||||
#ifndef CHANNEL_PRESENT
|
||||
#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
|
||||
#endif
|
||||
|
||||
//
|
||||
// Matches MrcDimmSts enum in MRC
|
||||
//
|
||||
#ifndef DIMM_ENABLED
|
||||
#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
|
||||
#endif
|
||||
#ifndef DIMM_DISABLED
|
||||
#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
|
||||
#endif
|
||||
#ifndef DIMM_PRESENT
|
||||
#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
|
||||
#endif
|
||||
#ifndef DIMM_NOT_PRESENT
|
||||
#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
|
||||
#endif
|
||||
|
||||
//
|
||||
// Matches MrcBootMode enum in MRC
|
||||
//
|
||||
#ifndef bmCold
|
||||
#define bmCold 0 // Cold boot
|
||||
#endif
|
||||
#ifndef bmWarm
|
||||
#define bmWarm 1 // Warm boot
|
||||
#endif
|
||||
#ifndef bmS3
|
||||
#define bmS3 2 // S3 resume
|
||||
#endif
|
||||
#ifndef bmFast
|
||||
#define bmFast 3 // Fast boot
|
||||
#endif
|
||||
|
||||
//
|
||||
// Matches MrcDdrType enum in MRC
|
||||
//
|
||||
#ifndef MRC_DDR_TYPE_DDR4
|
||||
#define MRC_DDR_TYPE_DDR4 0
|
||||
#endif
|
||||
#ifndef MRC_DDR_TYPE_DDR3
|
||||
#define MRC_DDR_TYPE_DDR3 1
|
||||
#endif
|
||||
#ifndef MRC_DDR_TYPE_LPDDR3
|
||||
#define MRC_DDR_TYPE_LPDDR3 2
|
||||
#endif
|
||||
#ifndef CPU_CFL//CNL
|
||||
#ifndef MRC_DDR_TYPE_LPDDR4
|
||||
#define MRC_DDR_TYPE_LPDDR4 3
|
||||
#endif
|
||||
#else//CFL
|
||||
#ifndef MRC_DDR_TYPE_UNKNOWN
|
||||
#define MRC_DDR_TYPE_UNKNOWN 3
|
||||
#endif
|
||||
#endif//CPU_CFL-endif
|
||||
|
||||
#define MAX_PROFILE_NUM 4 // number of memory profiles supported
|
||||
#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
|
||||
|
||||
//
|
||||
// DIMM timings
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 tCK; ///< Memory cycle time, in femtoseconds.
|
||||
UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
|
||||
UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
|
||||
UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
|
||||
UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
|
||||
UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
|
||||
UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
|
||||
UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
|
||||
UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
|
||||
UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
|
||||
UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
|
||||
UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
|
||||
UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
|
||||
UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
|
||||
UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
|
||||
UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
|
||||
UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
|
||||
UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
|
||||
UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
|
||||
} MRC_CH_TIMING;
|
||||
|
||||
typedef struct {
|
||||
UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.
|
||||
UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.
|
||||
UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).
|
||||
UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.
|
||||
} MRC_TA_TIMING;
|
||||
|
||||
///
|
||||
/// Memory SMBIOS & OC Memory Data Hob
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
|
||||
UINT8 DimmId;
|
||||
UINT32 DimmCapacity; ///< DIMM size in MBytes.
|
||||
UINT16 MfgId;
|
||||
UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
|
||||
UINT8 RankInDimm; ///< The number of ranks in this DIMM.
|
||||
UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
|
||||
UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
|
||||
UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
|
||||
UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
|
||||
UINT16 Speed; ///< The maximum capable speed of the device, in MHz.
|
||||
} DIMM_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Status; ///< Indicates whether this channel should be used.
|
||||
UINT8 ChannelId;
|
||||
UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
|
||||
MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
|
||||
DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
|
||||
MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings
|
||||
MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings
|
||||
MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings
|
||||
MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings
|
||||
} CHANNEL_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Status; ///< Indicates whether this controller should be used.
|
||||
UINT16 DeviceId; ///< The PCI device id of this memory controller.
|
||||
UINT8 RevisionId; ///< The PCI revision id of this memory controller.
|
||||
UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
|
||||
CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
|
||||
MRC_TA_TIMING tRd2Rd; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Read Turn Around Timings
|
||||
MRC_TA_TIMING tRd2Wr; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Write Turn Around Timings
|
||||
MRC_TA_TIMING tWr2Rd; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Read Turn Around Timings
|
||||
MRC_TA_TIMING tWr2Wr; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Write Turn Around Timings
|
||||
} CONTROLLER_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Revision;
|
||||
UINT16 DataWidth; ///< Data width, in bits, of this memory device
|
||||
/** As defined in SMBIOS 3.0 spec
|
||||
Section 7.18.2 and Table 75
|
||||
**/
|
||||
UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
|
||||
UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
|
||||
UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
|
||||
/** As defined in SMBIOS 3.0 spec
|
||||
Section 7.17.3 and Table 72
|
||||
**/
|
||||
UINT8 ErrorCorrectionType;
|
||||
|
||||
SiMrcVersion Version;
|
||||
BOOLEAN EccSupport;
|
||||
UINT8 MemoryProfile;
|
||||
UINT32 TotalPhysicalMemorySize;
|
||||
UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
|
||||
UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
|
||||
UINT8 Ratio;
|
||||
UINT8 RefClk;
|
||||
UINT32 VddVoltage[MAX_PROFILE_NUM];
|
||||
CONTROLLER_INFO Controller[MAX_NODE];
|
||||
} MEMORY_INFO_DATA_HOB;
|
||||
|
||||
/**
|
||||
Memory Platform Data Hob
|
||||
|
||||
<b>Revision 1:</b>
|
||||
- Initial version.
|
||||
<b>Revision 2:</b>
|
||||
- Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
|
||||
**/
|
||||
typedef struct {
|
||||
UINT8 Revision;
|
||||
UINT8 Reserved[3];
|
||||
UINT32 BootMode;
|
||||
UINT32 TsegSize;
|
||||
UINT32 TsegBase;
|
||||
UINT32 PrmrrSize;
|
||||
UINT32 PrmrrBase;
|
||||
UINT32 GttBase;
|
||||
UINT32 MmioSize;
|
||||
UINT32 PciEBaseAddress;
|
||||
#ifdef CPU_CFL
|
||||
UINT32 GdxcIotBase;
|
||||
UINT32 GdxcIotSize;
|
||||
UINT32 GdxcMotBase;
|
||||
UINT32 GdxcMotSize;
|
||||
#endif //CPU_CFL
|
||||
} MEMORY_PLATFORM_DATA;
|
||||
|
||||
typedef struct {
|
||||
EFI_HOB_GUID_TYPE EfiHobGuidType;
|
||||
MEMORY_PLATFORM_DATA Data;
|
||||
UINT8 *Buffer;
|
||||
} MEMORY_PLATFORM_DATA_HOB;
|
||||
|
||||
#pragma pack (pop)
|
||||
|
||||
#endif // _MEM_INFO_HOB_H_
|
||||
Loading…
Reference in New Issue