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soc/intel/alderlake: Fix value of SA_DEVFN_CPU_PCIE1_0 

The macro was defined using PCH_DEV_SLOT_CPU_1, which doesn't exist,
so replace it with the correct value of SA_DEV_SLOT_CPU_1.

Change-Id: If6d294d681907c51ac5678c9251364d4d6df4329
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Tim Wawrzynczak 2021-12-08 10:26:20 -07:00 committed by Felix Held
parent 3f5f1b5bff
commit 26e384bf34
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/alderlake/include/soc/pci_devs.h
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@ -26,7 +26,7 @@
#endif
#define SA_DEV_SLOT_CPU_1 0x01
#define SA_DEVFN_CPU_PCIE1_0 PCI_DEVFN(PCH_DEV_SLOT_CPU_1, 0)
#define SA_DEVFN_CPU_PCIE1_0 PCI_DEVFN(SA_DEV_SLOT_CPU_1, 0)
#define SA_DEV_SLOT_IGD 0x02
#define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0)