haswell: more ULT/LP support and minor tweaks
- Add ME device ID for Lynxpoint LP - Add GPU device IDs for ULT - SATA init tweaks from checking against DXE reference code - Remove the ICH7 from the SPI driver so it works on all lynxpoint without having to add more LPC device ID checks - Add function disable for audio dsp and xhci, remove PCI bridge - Add interrupt route registers for new devices (needs romstage setup) Change-Id: Idb48f50d0bacb6bf90531c3834542b9abb54fb8a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2680 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Duncan Laurie
Ronald G. Minnich
parent
eb58bc5af6
commit
26e7dd703d
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@ -40,14 +40,17 @@ u32 map_oprom_vendev(u32 vendev)
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case 0x80860402: /* GT1 Desktop */
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case 0x80860406: /* GT1 Mobile */
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case 0x8086040a: /* GT1 Server */
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case 0x80860a06: /* GT1 ULT */
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case 0x80860412: /* GT2 Desktop */
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case 0x80860416: /* GT2 Mobile */
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case 0x8086041a: /* GT2 Server */
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case 0x80860a16: /* GT2 ULT */
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case 0x80860422: /* GT3 Desktop */
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case 0x80860426: /* GT3 Mobile */
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case 0x8086042a: /* GT3 Server */
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case 0x80860a26: /* GT3 ULT */
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new_vendev=0x80860406; /* GT1 Mobile */
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break;
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@ -754,10 +754,16 @@ static struct device_operations device_ops = {
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.ops_pci = &pci_ops,
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};
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static const unsigned short pci_device_ids[] = {
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0x8c3a, /* Mobile */
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0x9c3a, /* Low Power */
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0
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};
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static const struct pci_driver intel_me __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x8c3a,
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.devices= pci_device_ids,
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};
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/******************************************************************************
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@ -55,6 +55,12 @@ int pch_silicon_supported(int type, int rev)
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static void pch_hide_devfn(unsigned devfn)
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{
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switch (devfn) {
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case PCI_DEVFN(19, 0): /* Audio DSP */
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RCBA32_OR(FD, PCH_DISABLE_ADSPD);
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break;
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case PCI_DEVFN(20, 0): /* XHCI */
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RCBA32_OR(FD, PCH_DISABLE_XHCI);
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break;
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case PCI_DEVFN(22, 0): /* MEI #1 */
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RCBA32_OR(FD2, PCH_DISABLE_MEI1);
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break;
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@ -89,9 +95,6 @@ static void pch_hide_devfn(unsigned devfn)
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case PCI_DEVFN(29, 0): /* EHCI #1 */
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RCBA32_OR(FD, PCH_DISABLE_EHCI1);
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break;
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case PCI_DEVFN(30, 0): /* PCI-to-PCI Bridge */
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RCBA32_OR(FD, PCH_DISABLE_P2P);
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break;
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case PCI_DEVFN(31, 0): /* LPC */
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RCBA32_OR(FD, PCH_DISABLE_LPC);
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break;
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@ -101,7 +104,7 @@ static void pch_hide_devfn(unsigned devfn)
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case PCI_DEVFN(31, 3): /* SMBUS */
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RCBA32_OR(FD, PCH_DISABLE_SMBUS);
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break;
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case PCI_DEVFN(31, 5): /* SATA #22 */
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case PCI_DEVFN(31, 5): /* SATA #2 */
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RCBA32_OR(FD, PCH_DISABLE_SATA2);
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break;
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case PCI_DEVFN(31, 6): /* Thermal Subsystem */
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@ -407,6 +407,8 @@ unsigned get_gpios(const int *gpio_num_array);
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#define D22IP_IDERIP 8 /* IDE-R Pin */
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#define D22IP_MEI2IP 4 /* MEI #2 Pin */
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#define D22IP_MEI1IP 0 /* MEI #1 Pin */
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#define D20IP 0x3128 /* 32bit */
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#define D20IP_XHCI 0 /* XHCI Pin */
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#define D31IR 0x3140 /* 16bit */
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#define D30IR 0x3142 /* 16bit */
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#define D29IR 0x3144 /* 16bit */
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@ -414,7 +416,11 @@ unsigned get_gpios(const int *gpio_num_array);
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#define D27IR 0x3148 /* 16bit */
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#define D26IR 0x314c /* 16bit */
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#define D25IR 0x3150 /* 16bit */
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#define D23IR 0x3158 /* 16bit */
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#define D22IR 0x315c /* 16bit */
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#define D20IR 0x3160 /* 16bit */
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#define D21IR 0x3164 /* 16bit */
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#define D19IR 0x3168 /* 16bit */
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#define OIC 0x31fe /* 16bit */
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#define SOFT_RESET_CTRL 0x38f4
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#define SOFT_RESET_DATA 0x38f8
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@ -434,8 +440,8 @@ unsigned get_gpios(const int *gpio_num_array);
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#define CG 0x341c /* 32bit */
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/* Function Disable 1 RCBA 0x3418 */
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#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)|(1 << 27))
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#define PCH_DISABLE_P2P (1 << 1)
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#define PCH_DISABLE_ALWAYS (1 << 0)
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#define PCH_DISABLE_ADSPD (1 << 1)
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#define PCH_DISABLE_SATA1 (1 << 2)
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#define PCH_DISABLE_SMBUS (1 << 3)
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#define PCH_DISABLE_HD_AUDIO (1 << 4)
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@ -445,6 +451,7 @@ unsigned get_gpios(const int *gpio_num_array);
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#define PCH_DISABLE_PCIE(x) (1 << (16 + x))
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#define PCH_DISABLE_THERMAL (1 << 24)
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#define PCH_DISABLE_SATA2 (1 << 25)
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#define PCH_DISABLE_XHCI (1 << 27)
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/* Function Disable 2 RCBA 0x3428 */
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#define PCH_DISABLE_KT (1 << 4)
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@ -23,6 +23,7 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <delay.h>
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#include "pch.h"
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typedef struct southbridge_intel_lynxpoint_config config_t;
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@ -123,6 +124,7 @@ static void sata_init(struct device *dev)
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reg16 &= ~0x3f;
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reg16 |= 0x8000 | config->sata_port_map;
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pci_write_config16(dev, 0x92, reg16);
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udelay(2);
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/* Setup register 98h */
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reg32 = pci_read_config16(dev, 0x98);
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@ -138,6 +140,7 @@ static void sata_init(struct device *dev)
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#if CONFIG_INTEL_LYNXPOINT_LP
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reg32 &= ~((1 << 31) | (1 << 30));
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reg32 |= 1 << 23;
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reg32 |= 1 << 24; /* Disable listen mode (hotplug) */
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#endif
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pci_write_config32(dev, 0x98, reg32);
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@ -159,6 +162,9 @@ static void sata_init(struct device *dev)
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reg32 = read32(abar + 0x00);
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reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
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reg32 &= ~0x00020060; // clear SXS+EMS+PMS
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#if CONFIG_INTEL_LYNXPOINT_LP
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reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY
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#endif
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write32(abar + 0x00, reg32);
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/* PI (Ports implemented) */
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write32(abar + 0x0c, config->sata_port_map);
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@ -166,12 +172,13 @@ static void sata_init(struct device *dev)
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(void) read32(abar + 0x0c); /* Read back 2 */
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/* CAP2 (HBA Capabilities Extended)*/
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reg32 = read32(abar + 0x24);
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#if CONFIG_INTEL_LYNXPOINT_LP
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/* Enable DEVSLP */
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reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2);
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#else
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reg32 &= ~0x00000002;
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#endif
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write32(abar + 0x24, reg32);
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/* VSP (Vendor Specific Register */
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reg32 = read32(abar + 0xa0);
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reg32 &= ~0x00000005;
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write32(abar + 0xa0, reg32);
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} else {
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printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
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@ -230,15 +237,33 @@ static void sata_init(struct device *dev)
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/* Additional Programming Requirements */
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/* Power Optimizer */
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sir_write(dev, 0x64, 0x883c9001);
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/* Step 1 */
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#if CONFIG_INTEL_LYNXPOINT_LP
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sir_write(dev, 0x64, 0x883c9003);
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#else
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sir_write(dev, 0x64, 0x883c9001);
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#endif
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/* Step 2: SIR 68h[15:0] = 880Ah */
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reg32 = sir_read(dev, 0x68);
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reg32 &= 0xffff0000;
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reg32 |= 0x880a;
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sir_write(dev, 0x68, reg32);
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/* Step 3: SIR 60h[3] = 1 */
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reg32 = sir_read(dev, 0x60);
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reg32 |= (1 << 0) | (1 << 1) | (1 << 3);
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reg32 |= (1 << 3);
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sir_write(dev, 0x60, reg32);
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/* Step 4: SIR 60h[0] = 1 */
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reg32 = sir_read(dev, 0x60);
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reg32 |= (1 << 0);
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sir_write(dev, 0x60, reg32);
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/* Step 5: SIR 60h[1] = 1 */
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reg32 = sir_read(dev, 0x60);
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reg32 |= (1 << 1);
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sir_write(dev, 0x60, reg32);
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/* Clock Gating */
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@ -68,18 +68,6 @@ typedef struct spi_slave ich_spi_slave;
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static int ichspi_lock = 0;
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typedef struct ich7_spi_regs {
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uint16_t spis;
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uint16_t spic;
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uint32_t spia;
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uint64_t spid[8];
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uint64_t _pad;
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uint32_t bbar;
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uint16_t preop;
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uint16_t optype;
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uint8_t opmenu[8];
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} __attribute__((packed)) ich7_spi_regs;
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typedef struct ich9_spi_regs {
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uint32_t bfpr;
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uint16_t hsfs;
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@ -302,110 +290,40 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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return slave;
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}
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/*
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* Check if this device ID matches one of supported Intel PCH devices.
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*
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* Return the ICH version if there is a match, or zero otherwise.
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*/
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static inline int get_ich_version(uint16_t device_id)
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{
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if (device_id >= PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MIN &&
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device_id <= PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_MAX)
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return 9;
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return 0;
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}
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void spi_init(void)
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{
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int ich_version = 0;
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uint8_t *rcrb; /* Root Complex Register Block */
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uint32_t rcba; /* Root Complex Base Address */
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uint8_t bios_cntl;
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device_t dev;
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uint32_t ids;
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uint16_t vendor_id, device_id;
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ich9_spi_regs *ich9_spi;
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#ifdef __SMM__
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dev = PCI_DEV(0, 31, 0);
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#else
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dev = dev_find_slot(0, PCI_DEVFN(31, 0));
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#endif
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pci_read_config_dword(dev, 0, &ids);
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vendor_id = ids;
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device_id = (ids >> 16);
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if (vendor_id != PCI_VENDOR_ID_INTEL) {
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printk(BIOS_DEBUG, "ICH SPI: No ICH found.\n");
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return;
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}
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ich_version = get_ich_version(device_id);
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if (!ich_version) {
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printk(BIOS_DEBUG, "ICH SPI: No known ICH found.\n");
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return;
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}
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pci_read_config_dword(dev, 0xf0, &rcba);
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/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
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rcrb = (uint8_t *)(rcba & 0xffffc000);
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switch (ich_version) {
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case 7:
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{
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const uint16_t ich7_spibar_offset = 0x3020;
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ich7_spi_regs *ich7_spi =
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(ich7_spi_regs *)(rcrb + ich7_spibar_offset);
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ichspi_lock = readw_(&ich7_spi->spis) & SPIS_LOCK;
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cntlr.opmenu = ich7_spi->opmenu;
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cntlr.menubytes = sizeof(ich7_spi->opmenu);
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cntlr.optype = &ich7_spi->optype;
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cntlr.addr = &ich7_spi->spia;
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cntlr.data = (uint8_t *)ich7_spi->spid;
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cntlr.databytes = sizeof(ich7_spi->spid);
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cntlr.status = (uint8_t *)&ich7_spi->spis;
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cntlr.control = &ich7_spi->spic;
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cntlr.bbar = &ich7_spi->bbar;
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cntlr.preop = &ich7_spi->preop;
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break;
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}
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case 9:
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{
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const uint16_t ich9_spibar_offset = 0x3800;
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ich9_spi_regs *ich9_spi =
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(ich9_spi_regs *)(rcrb + ich9_spibar_offset);
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ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN;
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cntlr.opmenu = ich9_spi->opmenu;
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cntlr.menubytes = sizeof(ich9_spi->opmenu);
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cntlr.optype = &ich9_spi->optype;
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cntlr.addr = &ich9_spi->faddr;
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cntlr.data = (uint8_t *)ich9_spi->fdata;
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cntlr.databytes = sizeof(ich9_spi->fdata);
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cntlr.status = &ich9_spi->ssfs;
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cntlr.control = (uint16_t *)ich9_spi->ssfc;
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cntlr.bbar = &ich9_spi->bbar;
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cntlr.preop = &ich9_spi->preop;
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break;
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}
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default:
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printk(BIOS_DEBUG, "ICH SPI: Unrecognized ICH version %d.\n", ich_version);
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}
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ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800);
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ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN;
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cntlr.opmenu = ich9_spi->opmenu;
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cntlr.menubytes = sizeof(ich9_spi->opmenu);
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cntlr.optype = &ich9_spi->optype;
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cntlr.addr = &ich9_spi->faddr;
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cntlr.data = (uint8_t *)ich9_spi->fdata;
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cntlr.databytes = sizeof(ich9_spi->fdata);
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cntlr.status = &ich9_spi->ssfs;
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cntlr.control = (uint16_t *)ich9_spi->ssfc;
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cntlr.bbar = &ich9_spi->bbar;
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cntlr.preop = &ich9_spi->preop;
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ich_set_bbar(0);
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/* Disable the BIOS write protect so write commands are allowed. */
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pci_read_config_byte(dev, 0xdc, &bios_cntl);
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switch (ich_version) {
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case 9:
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/* Deassert SMM BIOS Write Protect Disable. */
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bios_cntl &= ~(1 << 5);
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break;
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default:
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break;
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}
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bios_cntl &= ~(1 << 5);
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pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
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}
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