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snow: explicitly configure L2 cache 

This adds a call to explicitly configure L2 cache (though defaults
should be set correctly).

Change-Id: I120e29c986918c2904a0332e46fcf9f1c5380d85
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2950
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
David Hendricks 2013-03-28 19:05:29 -07:00
parent c01d138013
commit 26e8f2fe01
1 changed files with 2 additions and 0 deletions
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2
src/mainboard/google/snow/ramstage.c
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@ -21,6 +21,7 @@
#include <cbmem.h> #include <cbmem.h>
#include <arch/exception.h> #include <arch/exception.h>
#include <cpu/samsung/exynos5250/clk.h> #include <cpu/samsung/exynos5250/clk.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/power.h> #include <cpu/samsung/exynos5250/power.h>
#include <arch/cache.h> #include <arch/cache.h>
@ -45,6 +46,7 @@ void main(void)
/* set up dcache and MMU */ /* set up dcache and MMU */
/* FIXME: this should happen via resource allocator */ /* FIXME: this should happen via resource allocator */
exynos5250_config_l2_cache();
mmu_init(); mmu_init();
mmu_config_range(0, DRAM_START, DCACHE_OFF); mmu_config_range(0, DRAM_START, DCACHE_OFF);
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);