soc/braswell: Configure Boot Flash Write Protect status GPIO
Set up the GPIO(MF_ISH_GPIO_4) to read WP status. TEST=Use crossystem to read the WP status Signed-off-by: Hannah Williams <hannah.williams@intel.com> Change-Id: I17cbcba013e2a11c2527731df985aa1243065eff Original-Reviewed-on: https://chromium-review.googlesource.com/302424 Original-Tested-by: John Zhao <john.zhao@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/13185 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -242,7 +242,7 @@ static const struct soc_gpio_map gpe_gpio_map[] = {
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GPIO_NC, /* 19 MF_GPIO_5 */
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GPIO_NC, /* 20 MF_GPIO_9 */
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GPIO_NC, /* 21 MF_GPIO_0 */
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GPIO_NC, /* 22 MF_GPIO_4 */
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GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */
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GPIO_NC, /* 23 MF_GPIO_8 */
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GPIO_NC, /* 24 MF_GPIO_2 */
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GPIO_NC, /* 25 MF_GPIO_6 */
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