mb/lippert: Unify mainboards
Do it quick and dirty but in a reproducible manner. Variants will be set up properly in subsequent commits. Tested with BUILD_TIMELESS=1, both Lippert FrontRunner-AF and Toucan-AF remain identical. Change-Id: I71ff50099787e7806a9ab67429890a1c77061929 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43274 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
parent
bc9757ff17
commit
2719a451c3
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@ -1,13 +1,16 @@
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# SPDX-License-Identifier: GPL-2.0-only
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if BOARD_LIPPERT_FRONTRUNNER_AF
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if BOARD_LIPPERT_FRONTRUNNER_AF || BOARD_LIPPERT_TOUCAN_AF
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select CPU_AMD_AGESA_FAMILY14
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select NORTHBRIDGE_AMD_AGESA_FAMILY14
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select SOUTHBRIDGE_AMD_CIMX_SB800
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select SUPERIO_SMSC_SMSCSUPERIO
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select SUPERIO_SMSC_SMSCSUPERIO if BOARD_LIPPERT_FRONTRUNNER_AF
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# The Toucan-AF is meant to work on any COM Express Type 6 baseboard.
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# The ADLINK ExpressBase-6 baseboard happens to use this SIO:
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select SUPERIO_WINBOND_W83627DHG if BOARD_LIPPERT_TOUCAN_AF
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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@ -22,9 +25,20 @@ config MAINBOARD_DIR
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string
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default "lippert/frontrunner-af"
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config VARIANT_DIR
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string
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default "frontrunner-af" if BOARD_LIPPERT_FRONTRUNNER_AF
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default "toucan-af" if BOARD_LIPPERT_TOUCAN_AF
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config DEVICETREE
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string
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default "devicetree-fr.cb" if BOARD_LIPPERT_FRONTRUNNER_AF
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default "devicetree-tc.cb" if BOARD_LIPPERT_TOUCAN_AF
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config MAINBOARD_PART_NUMBER
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string
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default "FrontRunner-AF"
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default "FrontRunner-AF" if BOARD_LIPPERT_FRONTRUNNER_AF
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default "Toucan-AF" if BOARD_LIPPERT_TOUCAN_AF
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config HW_MEM_HOLE_SIZEK
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hex
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@ -54,4 +68,4 @@ config SB800_AHCI_ROM
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bool
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default n
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endif # BOARD_LIPPERT_FRONTRUNNER_AF
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endif # BOARD_LIPPERT_FRONTRUNNER_AF || BOARD_LIPPERT_TOUCAN_AF
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@ -1,2 +1,5 @@
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config BOARD_LIPPERT_FRONTRUNNER_AF
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bool "FrontRunner-AF aka ADLINK CoreModule2-GF"
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config BOARD_LIPPERT_TOUCAN_AF
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bool "Toucan-AF aka cExpress-GFR (+W83627DHG SIO)"
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@ -7,15 +7,31 @@ pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FI
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pci$(stripped_ahcibios_id).rom-type := optionrom
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endif
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bootblock-y += bootblock.c
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ifeq ($(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF),y)
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bootblock-y += bootblock-fr.c
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else ifeq ($(CONFIG_BOARD_LIPPERT_TOUCAN_AF),y)
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bootblock-y += bootblock-tc.c
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endif
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romstage-y += buildOpts.c
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romstage-y += BiosCallOuts.c
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romstage-y += OemCustomize.c
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ifeq ($(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF),y)
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romstage-y += BiosCallOuts-fr.c
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romstage-y += OemCustomize-fr.c
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else ifeq ($(CONFIG_BOARD_LIPPERT_TOUCAN_AF),y)
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romstage-y += BiosCallOuts-tc.c
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romstage-y += OemCustomize-tc.c
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endif
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ramstage-y += buildOpts.c
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ramstage-y += BiosCallOuts.c
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ramstage-y += OemCustomize.c
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ifeq ($(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF),y)
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ramstage-y += BiosCallOuts-fr.c
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ramstage-y += OemCustomize-fr.c
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ramstage-y += mainboard-fr.c
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else ifeq ($(CONFIG_BOARD_LIPPERT_TOUCAN_AF),y)
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ramstage-y += BiosCallOuts-tc.c
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ramstage-y += OemCustomize-tc.c
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ramstage-y += mainboard-tc.c
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endif
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# Minimal SEMA watchdog support
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romstage-y += sema.c
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@ -365,6 +365,7 @@ Scope(\_SB) {
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})
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Name(PCIB, Package(){
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#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF)
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/* PCI slots: slot 0, slot 1, slot 2, slot 3 behind Dev14, Fun4. */
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Package(){0x0004FFFF, 0, 0, 0x14 },
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Package(){0x0004FFFF, 1, 0, 0x15 },
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@ -382,5 +383,20 @@ Scope(\_SB) {
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Package(){0x0007FFFF, 1, 0, 0x14 },
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Package(){0x0007FFFF, 2, 0, 0x15 },
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Package(){0x0007FFFF, 3, 0, 0x16 },
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#elif CONFIG(BOARD_LIPPERT_TOUCAN_AF)
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/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
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Package(){0x0003FFFF, 0, 0, 0x14 },
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Package(){0x0003FFFF, 1, 0, 0x15 },
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Package(){0x0003FFFF, 2, 0, 0x16 },
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Package(){0x0003FFFF, 3, 0, 0x17 },
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Package(){0x0004FFFF, 0, 0, 0x15 },
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Package(){0x0004FFFF, 1, 0, 0x16 },
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Package(){0x0004FFFF, 2, 0, 0x17 },
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Package(){0x0004FFFF, 3, 0, 0x14 },
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Package(){0x0005FFFF, 0, 0, 0x16 },
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Package(){0x0005FFFF, 1, 0, 0x17 },
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Package(){0x0005FFFF, 2, 0, 0x14 },
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Package(){0x0005FFFF, 3, 0, 0x15 },
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#endif
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})
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}
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@ -1,5 +1,4 @@
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Category: half
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Board URL: http://www.adlinktech.com/PD/web/PD_detail.php?pid=1277
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ROM package: SOIC8
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ROM protocol: SPI
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ROM socketed: n
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@ -1174,7 +1174,9 @@ DefinitionBlock (
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,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */
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IO(Decode16, 0x004E, 0x004E, 1, 2) /* SIO config regs */
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#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF)
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IO(Decode16, 0x0E00, 0x0E00, 1, 0x80) /* SIO runtime regs */
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#endif
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IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
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WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
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@ -45,7 +45,11 @@
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* Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5
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* Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6
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*/
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#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF)
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#define USB_CONFIG 0x3F
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#elif CONFIG(BOARD_LIPPERT_TOUCAN_AF)
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#define USB_CONFIG 0x0F
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#endif
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/**
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* @def PCI_CLOCK_CTRL
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@ -58,7 +62,11 @@
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* PCI SLOT 3 define at BIT3
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* PCI SLOT 4 define at BIT4
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*/
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#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF)
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#define PCI_CLOCK_CTRL 0x1F
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#elif CONFIG(BOARD_LIPPERT_TOUCAN_AF)
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#define PCI_CLOCK_CTRL 0x1E
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#endif
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/**
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* @def SATA_CONTROLLER
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@ -148,12 +156,20 @@
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* SDIN2 is define at BIT4 & BIT5
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* SDIN3 is define at BIT6 & BIT7
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*/
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#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF)
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#define AZALIA_SDIN_PIN 0x02
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#elif CONFIG(BOARD_LIPPERT_TOUCAN_AF)
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#define AZALIA_SDIN_PIN 0x2A
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#endif
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/**
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* @def GPP_CONTROLLER
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*/
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#if CONFIG(BOARD_LIPPERT_FRONTRUNNER_AF)
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#define GPP_CONTROLLER CIMX_OPTION_DISABLED
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#elif CONFIG(BOARD_LIPPERT_TOUCAN_AF)
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#define GPP_CONTROLLER CIMX_OPTION_ENABLED
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#endif
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/**
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* @def GPP_CFGMODE
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@ -0,0 +1,5 @@
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Category: half
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ROM package: SOIC8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -1,64 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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if BOARD_LIPPERT_TOUCAN_AF
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select CPU_AMD_AGESA_FAMILY14
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select NORTHBRIDGE_AMD_AGESA_FAMILY14
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select SOUTHBRIDGE_AMD_CIMX_SB800
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# The Toucan-AF is meant to work on any COM Express Type 6 baseboard.
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# The ADLINK ExpressBase-6 baseboard happens to use this SIO:
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select SUPERIO_WINBOND_W83627DHG
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select HAVE_OPTION_TABLE
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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# This erases 28 KB and writes 10 KB register dumps to SPI flash on every
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# boot, wasting 3 s and causing wear! Therefore disable S3 for now.
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#select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_4096
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select GFXUMA
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config MAINBOARD_DIR
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string
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default "lippert/toucan-af"
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config MAINBOARD_PART_NUMBER
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string
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default "Toucan-AF"
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x200000
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config MAX_CPUS
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int
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default 2
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config IRQ_SLOT_COUNT
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int
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default 11
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config ONBOARD_VGA_IS_PRIMARY
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bool
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default y
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config VGA_BIOS
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bool
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default n
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#config VGA_BIOS_FILE
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# string "VGA BIOS path and filename"
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# depends on VGA_BIOS
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# default "rom/video/OntarioGenericVbios.bin"
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config VGA_BIOS_ID
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string
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default "1002,9802"
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config SB800_AHCI_ROM
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bool
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default n
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endif # BOARD_LIPPERT_TOUCAN_AF
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@ -1,2 +0,0 @@
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config BOARD_LIPPERT_TOUCAN_AF
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bool "Toucan-AF aka cExpress-GFR (+W83627DHG SIO)"
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@ -1,22 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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ifeq ($(CONFIG_AHCI_BIOS),y)
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stripped_ahcibios_id = $(call strip_quotes,$(CONFIG_AHCI_BIOS_ID))
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cbfs-files-$(CONFIG_AHCI_BIOS) += pci$(stripped_ahcibios_id).rom
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pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FILE))
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pci$(stripped_ahcibios_id).rom-type := optionrom
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endif
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bootblock-y += bootblock.c
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romstage-y += buildOpts.c
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romstage-y += BiosCallOuts.c
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romstage-y += OemCustomize.c
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ramstage-y += buildOpts.c
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ramstage-y += BiosCallOuts.c
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ramstage-y += OemCustomize.c
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# Minimal SEMA watchdog support
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romstage-y += ../frontrunner-af/sema.c
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ramstage-y += ../frontrunner-af/sema.c
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@ -1,43 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/**
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* @file
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*
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* IDS Option File
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*
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* This file is used to switch on/off IDS features.
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*
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*/
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#ifndef _OPTION_IDS_H_
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#define _OPTION_IDS_H_
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/**
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*
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* This file generates the defaults tables for the Integrated Debug Support
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* Module. The documented build options are imported from a user controlled
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* file for processing. The build options for the Integrated Debug Support
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* Module are listed below:
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*
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* IDSOPT_IDS_ENABLED
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* IDSOPT_ERROR_TRAP_ENABLED
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* IDSOPT_CONTROL_ENABLED
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* IDSOPT_TRACING_ENABLED
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* IDSOPT_PERF_ANALYSIS
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* IDSOPT_ASSERT_ENABLED
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* IDS_DEBUG_PORT
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* IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
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*
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**/
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#define IDSOPT_IDS_ENABLED TRUE
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//#define IDSOPT_TRACING_ENABLED TRUE
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#define IDSOPT_ASSERT_ENABLED TRUE
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//#define IDSOPT_DEBUG_ENABLED FALSE
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//#undef IDSOPT_HOST_SIMNOW
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//#define IDSOPT_HOST_SIMNOW FALSE
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//#undef IDSOPT_HOST_HDT
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//#define IDSOPT_HOST_HDT FALSE
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//#define IDS_DEBUG_PORT 0x80
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#endif
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@ -1,382 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Routing is in System Bus scope */
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Scope(\_SB) {
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Name(PR0, Package(){
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/* NB devices */
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/* Bus 0, Dev 0 - RS780 Host Controller */
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/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
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Package(){0x0001FFFF, 0, INTC, 0 },
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Package(){0x0001FFFF, 1, INTD, 0 },
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/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
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Package(){0x0002FFFF, 0, INTC, 0 },
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Package(){0x0002FFFF, 1, INTD, 0 },
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Package(){0x0002FFFF, 2, INTA, 0 },
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Package(){0x0002FFFF, 3, INTB, 0 },
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/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
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Package(){0x0003FFFF, 0, INTD, 0 },
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Package(){0x0003FFFF, 1, INTA, 0 },
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Package(){0x0003FFFF, 2, INTB, 0 },
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Package(){0x0003FFFF, 3, INTC, 0 },
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/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
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Package(){0x0004FFFF, 0, INTA, 0 },
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Package(){0x0004FFFF, 1, INTB, 0 },
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Package(){0x0004FFFF, 2, INTC, 0 },
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Package(){0x0004FFFF, 3, INTD, 0 },
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/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
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Package(){0x0005FFFF, 0, INTB, 0 },
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Package(){0x0005FFFF, 1, INTC, 0 },
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Package(){0x0005FFFF, 2, INTD, 0 },
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Package(){0x0005FFFF, 3, INTA, 0 },
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/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
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Package(){0x0006FFFF, 0, INTC, 0 },
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Package(){0x0006FFFF, 1, INTD, 0 },
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Package(){0x0006FFFF, 2, INTA, 0 },
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Package(){0x0006FFFF, 3, INTB, 0 },
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/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
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Package(){0x0007FFFF, 0, INTD, 0 },
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Package(){0x0007FFFF, 1, INTA, 0 },
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Package(){0x0007FFFF, 2, INTB, 0 },
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Package(){0x0007FFFF, 3, INTC, 0 },
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Package(){0x0009FFFF, 0, INTB, 0 },
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Package(){0x0009FFFF, 1, INTC, 0 },
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Package(){0x0009FFFF, 2, INTD, 0 },
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Package(){0x0009FFFF, 3, INTA, 0 },
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Package(){0x000AFFFF, 0, INTC, 0 },
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Package(){0x000AFFFF, 1, INTD, 0 },
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Package(){0x000AFFFF, 2, INTA, 0 },
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Package(){0x000AFFFF, 3, INTB, 0 },
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Package(){0x000BFFFF, 0, INTD, 0 },
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Package(){0x000BFFFF, 1, INTA, 0 },
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Package(){0x000BFFFF, 2, INTB, 0 },
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Package(){0x000BFFFF, 3, INTC, 0 },
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Package(){0x000CFFFF, 0, INTA, 0 },
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Package(){0x000CFFFF, 1, INTB, 0 },
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Package(){0x000CFFFF, 2, INTC, 0 },
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Package(){0x000CFFFF, 3, INTD, 0 },
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/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
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/* SB devices */
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/* Bus 0, Dev 17 - SATA controller #2 */
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/* Bus 0, Dev 18 - SATA controller #1 */
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Package(){0x0011FFFF, 0, INTD, 0 },
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/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
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* EHCI, dev 18, 19 func 2 */
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Package(){0x0012FFFF, 0, INTC, 0 },
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Package(){0x0012FFFF, 1, INTB, 0 },
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Package(){0x0013FFFF, 0, INTC, 0 },
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Package(){0x0013FFFF, 1, INTB, 0 },
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Package(){0x0016FFFF, 0, INTC, 0 },
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Package(){0x0016FFFF, 1, INTB, 0 },
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/* Package(){0x0014FFFF, 1, INTA, 0 }, */
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/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
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Package(){0x0014FFFF, 0, INTA, 0 },
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Package(){0x0014FFFF, 1, INTB, 0 },
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Package(){0x0014FFFF, 2, INTC, 0 },
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Package(){0x0014FFFF, 3, INTD, 0 },
|
||||
|
||||
Package(){0x0015FFFF, 0, INTA, 0 },
|
||||
Package(){0x0015FFFF, 1, INTB, 0 },
|
||||
Package(){0x0015FFFF, 2, INTC, 0 },
|
||||
Package(){0x0015FFFF, 3, INTD, 0 },
|
||||
})
|
||||
|
||||
Name(APR0, Package(){
|
||||
/* NB devices in APIC mode */
|
||||
/* Bus 0, Dev 0 - RS780 Host Controller */
|
||||
|
||||
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
|
||||
Package(){0x0001FFFF, 0, 0, 18 },
|
||||
Package(){0x0001FFFF, 1, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
|
||||
Package(){0x0002FFFF, 0, 0, 18 },
|
||||
/* Package(){0x0002FFFF, 1, 0, 19 }, */
|
||||
/* Package(){0x0002FFFF, 2, 0, 16 }, */
|
||||
/* Package(){0x0002FFFF, 3, 0, 17 }, */
|
||||
|
||||
/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
|
||||
Package(){0x0003FFFF, 0, 0, 19 },
|
||||
Package(){0x0003FFFF, 1, 0, 16 },
|
||||
Package(){0x0003FFFF, 2, 0, 17 },
|
||||
Package(){0x0003FFFF, 3, 0, 18 },
|
||||
|
||||
/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
|
||||
Package(){0x0004FFFF, 0, 0, 16 },
|
||||
Package(){0x0004FFFF, 1, 0, 17 },
|
||||
Package(){0x0004FFFF, 2, 0, 18 },
|
||||
Package(){0x0004FFFF, 3, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
|
||||
Package(){0x0005FFFF, 0, 0, 17 },
|
||||
Package(){0x0005FFFF, 1, 0, 18 },
|
||||
Package(){0x0005FFFF, 2, 0, 19 },
|
||||
Package(){0x0005FFFF, 3, 0, 16 },
|
||||
|
||||
/* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
|
||||
Package(){0x0006FFFF, 0, 0, 18 },
|
||||
Package(){0x0006FFFF, 1, 0, 19 },
|
||||
Package(){0x0006FFFF, 2, 0, 16 },
|
||||
Package(){0x0006FFFF, 3, 0, 17 },
|
||||
|
||||
/* Bus 0, Dev 7 - PCIe Bridge for network card */
|
||||
Package(){0x0007FFFF, 0, 0, 19 },
|
||||
Package(){0x0007FFFF, 1, 0, 16 },
|
||||
Package(){0x0007FFFF, 2, 0, 17 },
|
||||
Package(){0x0007FFFF, 3, 0, 18 },
|
||||
|
||||
/* Bus 0, Dev 9 - PCIe Bridge for network card */
|
||||
Package(){0x0009FFFF, 0, 0, 17 },
|
||||
Package(){0x0009FFFF, 1, 0, 16 },
|
||||
Package(){0x0009FFFF, 2, 0, 17 },
|
||||
Package(){0x0009FFFF, 3, 0, 18 },
|
||||
/* Bus 0, Dev A - PCIe Bridge for network card */
|
||||
Package(){0x000AFFFF, 0, 0, 18 },
|
||||
Package(){0x000AFFFF, 1, 0, 16 },
|
||||
Package(){0x000AFFFF, 2, 0, 17 },
|
||||
Package(){0x000AFFFF, 3, 0, 18 },
|
||||
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
|
||||
|
||||
/* SB devices in APIC mode */
|
||||
/* Bus 0, Dev 17 - SATA controller #2 */
|
||||
/* Bus 0, Dev 18 - SATA controller #1 */
|
||||
Package(){0x0011FFFF, 0, 0, 19 },
|
||||
|
||||
/* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
|
||||
* EHCI, dev 18, 19 func 2 */
|
||||
Package(){0x0012FFFF, 0, 0, 18 },
|
||||
Package(){0x0012FFFF, 1, 0, 17 },
|
||||
/* Package(){0x0012FFFF, 2, 0, 18 }, */
|
||||
|
||||
Package(){0x0013FFFF, 0, 0, 18 },
|
||||
Package(){0x0013FFFF, 1, 0, 17 },
|
||||
/* Package(){0x0013FFFF, 2, 0, 16 }, */
|
||||
|
||||
/* Package(){0x00140000, 0, 0, 16 }, */
|
||||
|
||||
Package(){0x0016FFFF, 0, 0, 18 },
|
||||
Package(){0x0016FFFF, 1, 0, 17 },
|
||||
|
||||
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
/* Package(){0x00140004, 2, 0, 18 }, */
|
||||
/* Package(){0x00140004, 3, 0, 19 }, */
|
||||
/* Package(){0x00140005, 1, 0, 17 }, */
|
||||
/* Package(){0x00140006, 1, 0, 17 }, */
|
||||
|
||||
/* TODO: pcie */
|
||||
Package(){0x0015FFFF, 0, 0, 16 },
|
||||
Package(){0x0015FFFF, 1, 0, 17 },
|
||||
Package(){0x0015FFFF, 2, 0, 18 },
|
||||
Package(){0x0015FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, INTA, 0 },
|
||||
Package(){0x0005FFFF, 1, INTB, 0 },
|
||||
Package(){0x0005FFFF, 2, INTC, 0 },
|
||||
Package(){0x0005FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APR1, Package(){
|
||||
/* Internal graphics - RS780 VGA, Bus1, Dev5 */
|
||||
Package(){0x0005FFFF, 0, 0, 18 },
|
||||
Package(){0x0005FFFF, 1, 0, 19 },
|
||||
/* Package(){0x0005FFFF, 2, 0, 20 }, */
|
||||
/* Package(){0x0005FFFF, 3, 0, 17 }, */
|
||||
})
|
||||
|
||||
Name(PS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS2, Package(){
|
||||
/* The external GFX - Hooked to PCIe slot 2 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APS4, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 4 */
|
||||
Package(){0x0000FFFF, 0, 0, 16 },
|
||||
Package(){0x0000FFFF, 1, 0, 17 },
|
||||
Package(){0x0000FFFF, 2, 0, 18 },
|
||||
Package(){0x0000FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
Name(APS5, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 5 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APS6, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 6 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APS7, Package(){
|
||||
/* The onboard Ethernet chip - Hooked to PCIe slot 7 */
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
|
||||
Name(PS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 9 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APS9, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 9 */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PSa, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APSa, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PE0, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTA, 0 },
|
||||
Package(){0x0000FFFF, 1, INTB, 0 },
|
||||
Package(){0x0000FFFF, 2, INTC, 0 },
|
||||
Package(){0x0000FFFF, 3, INTD, 0 },
|
||||
})
|
||||
Name(APE0, Package(){
|
||||
/* PCIe slot - Hooked to PCIe */
|
||||
Package(){0x0000FFFF, 0, 0, 16 },
|
||||
Package(){0x0000FFFF, 1, 0, 17 },
|
||||
Package(){0x0000FFFF, 2, 0, 18 },
|
||||
Package(){0x0000FFFF, 3, 0, 19 },
|
||||
})
|
||||
|
||||
Name(PE1, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTB, 0 },
|
||||
Package(){0x0000FFFF, 1, INTC, 0 },
|
||||
Package(){0x0000FFFF, 2, INTD, 0 },
|
||||
Package(){0x0000FFFF, 3, INTA, 0 },
|
||||
})
|
||||
Name(APE1, Package(){
|
||||
/* PCIe slot - Hooked to PCIe */
|
||||
Package(){0x0000FFFF, 0, 0, 17 },
|
||||
Package(){0x0000FFFF, 1, 0, 18 },
|
||||
Package(){0x0000FFFF, 2, 0, 19 },
|
||||
Package(){0x0000FFFF, 3, 0, 16 },
|
||||
})
|
||||
|
||||
Name(PE2, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTC, 0 },
|
||||
Package(){0x0000FFFF, 1, INTD, 0 },
|
||||
Package(){0x0000FFFF, 2, INTA, 0 },
|
||||
Package(){0x0000FFFF, 3, INTB, 0 },
|
||||
})
|
||||
Name(APE2, Package(){
|
||||
/* PCIe slot - Hooked to PCIe */
|
||||
Package(){0x0000FFFF, 0, 0, 18 },
|
||||
Package(){0x0000FFFF, 1, 0, 19 },
|
||||
Package(){0x0000FFFF, 2, 0, 16 },
|
||||
Package(){0x0000FFFF, 3, 0, 17 },
|
||||
})
|
||||
|
||||
Name(PE3, Package(){
|
||||
/* PCIe slot - Hooked to PCIe slot 10 */
|
||||
Package(){0x0000FFFF, 0, INTD, 0 },
|
||||
Package(){0x0000FFFF, 1, INTA, 0 },
|
||||
Package(){0x0000FFFF, 2, INTB, 0 },
|
||||
Package(){0x0000FFFF, 3, INTC, 0 },
|
||||
})
|
||||
Name(APE3, Package(){
|
||||
/* PCIe slot - Hooked to PCIe */
|
||||
Package(){0x0000FFFF, 0, 0, 19 },
|
||||
Package(){0x0000FFFF, 1, 0, 16 },
|
||||
Package(){0x0000FFFF, 2, 0, 17 },
|
||||
Package(){0x0000FFFF, 3, 0, 18 },
|
||||
})
|
||||
|
||||
Name(PCIB, Package(){
|
||||
/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
|
||||
Package(){0x0003FFFF, 0, 0, 0x14 },
|
||||
Package(){0x0003FFFF, 1, 0, 0x15 },
|
||||
Package(){0x0003FFFF, 2, 0, 0x16 },
|
||||
Package(){0x0003FFFF, 3, 0, 0x17 },
|
||||
Package(){0x0004FFFF, 0, 0, 0x15 },
|
||||
Package(){0x0004FFFF, 1, 0, 0x16 },
|
||||
Package(){0x0004FFFF, 2, 0, 0x17 },
|
||||
Package(){0x0004FFFF, 3, 0, 0x14 },
|
||||
Package(){0x0005FFFF, 0, 0, 0x16 },
|
||||
Package(){0x0005FFFF, 1, 0, 0x17 },
|
||||
Package(){0x0005FFFF, 2, 0, 0x14 },
|
||||
Package(){0x0005FFFF, 3, 0, 0x15 },
|
||||
})
|
||||
}
|
||||
|
|
@ -1,132 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* simple name description */
|
||||
|
||||
/*
|
||||
Scope (_SB) {
|
||||
Device(PCI0) {
|
||||
Device(SATA) {
|
||||
Name(_ADR, 0x00110000)
|
||||
#include "sata.asl"
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
Name(STTM, Buffer(20) {
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
|
||||
0x1f, 0x00, 0x00, 0x00
|
||||
})
|
||||
|
||||
/* Start by clearing the PhyRdyChg bits */
|
||||
Method(_INI) {
|
||||
\_GPE._L1F()
|
||||
}
|
||||
|
||||
Device(PMRY)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(PMST) {
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P0IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
}/* end of PMST */
|
||||
|
||||
Device(PSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P1IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of PSLA */
|
||||
} /* end of PMRY */
|
||||
|
||||
|
||||
Device(SEDY)
|
||||
{
|
||||
Name(_ADR, 1) /* IDE Scondary Channel */
|
||||
Method(_GTM, 0x0, NotSerialized) {
|
||||
Return(STTM)
|
||||
}
|
||||
Method(_STM, 0x3, NotSerialized) {}
|
||||
|
||||
Device(SMST)
|
||||
{
|
||||
Name(_ADR, 0)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P2IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SMST */
|
||||
|
||||
Device(SSLA)
|
||||
{
|
||||
Name(_ADR, 1)
|
||||
Method(_STA,0) {
|
||||
if (LGreater(P3IS,0)) {
|
||||
return (0x0F) /* sata is visible */
|
||||
}
|
||||
else {
|
||||
return (0x00) /* sata is missing */
|
||||
}
|
||||
}
|
||||
} /* end of SSLA */
|
||||
} /* end of SEDY */
|
||||
|
||||
/* SATA Hot Plug Support */
|
||||
Scope(\_GPE) {
|
||||
Method(_L1F,0x0,NotSerialized) {
|
||||
if (\_SB.P0PR) {
|
||||
if (LGreater(\_SB.P0IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P0PR)
|
||||
}
|
||||
|
||||
if (\_SB.P1PR) {
|
||||
if (LGreater(\_SB.P1IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P1PR)
|
||||
}
|
||||
|
||||
if (\_SB.P2PR) {
|
||||
if (LGreater(\_SB.P2IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P2PR)
|
||||
}
|
||||
|
||||
if (\_SB.P3PR) {
|
||||
if (LGreater(\_SB.P3IS,0)) {
|
||||
sleep(32)
|
||||
}
|
||||
Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
|
||||
store(one, \_SB.P3PR)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/*
|
||||
* SuperI/O devices
|
||||
*/
|
||||
|
||||
/* PS/2 Keyboard */
|
||||
Device(KBC) {
|
||||
Name(_HID, EISAID("PNP0303"))
|
||||
Name(_CRS, ResourceTemplate() {
|
||||
IO(Decode16, 0x0060, 0x0060, 1, 1)
|
||||
IO(Decode16, 0x0064, 0x0064, 1, 1)
|
||||
IRQNoFlags(){1}
|
||||
})
|
||||
}
|
||||
|
||||
/* PS/2 Mouse */
|
||||
Device(PS2M) {
|
||||
Name(_HID, EISAID("PNP0F13"))
|
||||
Name(_CRS, ResourceTemplate() {
|
||||
IRQNoFlags(){12}
|
||||
})
|
||||
}
|
||||
|
|
@ -1,136 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
Method(UCOC, 0) {
|
||||
Sleep(20)
|
||||
Store(0x13,CMTI)
|
||||
Store(0,GPSL)
|
||||
}
|
||||
|
||||
/* USB Port 0 overcurrent uses Gpm 0 */
|
||||
If(LLessEqual(UOM0,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L13) {
|
||||
UCOC()
|
||||
if(LEqual(GPB0,PLC0)) {
|
||||
Not(PLC0,PLC0)
|
||||
Store(PLC0, \_SB.PT0D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 1 overcurrent uses Gpm 1 */
|
||||
If (LLessEqual(UOM1,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L14) {
|
||||
UCOC()
|
||||
if (LEqual(GPB1,PLC1)) {
|
||||
Not(PLC1,PLC1)
|
||||
Store(PLC1, \_SB.PT1D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 2 overcurrent uses Gpm 2 */
|
||||
If (LLessEqual(UOM2,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L15) {
|
||||
UCOC()
|
||||
if (LEqual(GPB2,PLC2)) {
|
||||
Not(PLC2,PLC2)
|
||||
Store(PLC2, \_SB.PT2D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 3 overcurrent uses Gpm 3 */
|
||||
If (LLessEqual(UOM3,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L16) {
|
||||
UCOC()
|
||||
if (LEqual(GPB3,PLC3)) {
|
||||
Not(PLC3,PLC3)
|
||||
Store(PLC3, \_SB.PT3D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 4 overcurrent uses Gpm 4 */
|
||||
If (LLessEqual(UOM4,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L19) {
|
||||
UCOC()
|
||||
if (LEqual(GPB4,PLC4)) {
|
||||
Not(PLC4,PLC4)
|
||||
Store(PLC4, \_SB.PT4D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 5 overcurrent uses Gpm 5 */
|
||||
If (LLessEqual(UOM5,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L1A) {
|
||||
UCOC()
|
||||
if (LEqual(GPB5,PLC5)) {
|
||||
Not(PLC5,PLC5)
|
||||
Store(PLC5, \_SB.PT5D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 6 overcurrent uses Gpm 6 */
|
||||
If (LLessEqual(UOM6,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1C) { */
|
||||
Method (_L06) {
|
||||
UCOC()
|
||||
if (LEqual(GPB6,PLC6)) {
|
||||
Not(PLC6,PLC6)
|
||||
Store(PLC6, \_SB.PT6D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 7 overcurrent uses Gpm 7 */
|
||||
If (LLessEqual(UOM7,9)) {
|
||||
Scope (\_GPE) {
|
||||
/* Method (_L1D) { */
|
||||
Method (_L07) {
|
||||
UCOC()
|
||||
if (LEqual(GPB7,PLC7)) {
|
||||
Not(PLC7,PLC7)
|
||||
Store(PLC7, \_SB.PT7D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 8 overcurrent uses Gpm 8 */
|
||||
If (LLessEqual(UOM8,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L17) {
|
||||
if (LEqual(G8IS,PLC8)) {
|
||||
Not(PLC8,PLC8)
|
||||
Store(PLC8, \_SB.PT8D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* USB Port 9 overcurrent uses Gpm 9 */
|
||||
If (LLessEqual(UOM9,9)) {
|
||||
Scope (\_GPE) {
|
||||
Method (_L0E) {
|
||||
if (LEqual(G9IS,0)) {
|
||||
Store(1,\_SB.PT9D)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
#include <arch/ioapic.h>
|
||||
|
||||
unsigned long acpi_fill_madt(unsigned long current)
|
||||
{
|
||||
/* create all subtables for processors */
|
||||
current = acpi_create_madt_lapics(current);
|
||||
|
||||
/* Write SB800 IOAPIC, only one */
|
||||
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
|
||||
CONFIG_MAX_CPUS, IO_APIC_ADDR, 0);
|
||||
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 0, 2, 0);
|
||||
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
|
||||
current, 0, 9, 9, 0xF);
|
||||
|
||||
/* 0: mean bus 0--->ISA */
|
||||
/* 0: PIC 0 */
|
||||
/* 2: APIC 2 */
|
||||
/* 5 mean: 0101 --> Edge-triggered, Active high */
|
||||
|
||||
/* create all subtables for processors */
|
||||
/* current = acpi_create_madt_lapic_nmis(current, 5, 1); */
|
||||
/* 1: LINT1 connect to NMI */
|
||||
|
||||
return current;
|
||||
}
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* Select the CPU family */
|
||||
#define INSTALL_FAMILY_14_SUPPORT TRUE
|
||||
|
||||
/* Select the CPU socket type */
|
||||
#define INSTALL_FT1_SOCKET_SUPPORT TRUE
|
||||
|
||||
/* Agesa optional capabilities selection */
|
||||
#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE
|
||||
#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
|
||||
#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE
|
||||
#define BLDOPT_REMOVE_ECC_SUPPORT FALSE
|
||||
#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE
|
||||
#define BLDOPT_REMOVE_WHEA FALSE
|
||||
|
||||
#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1
|
||||
|
||||
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
|
||||
#define BLDCFG_CFG_GNB_HD_AUDIO FALSE
|
||||
#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
|
||||
#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE
|
||||
#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE
|
||||
|
||||
/* Agesa configuration values selection */
|
||||
#include <AGESA.h>
|
||||
|
||||
/* Include the files that instantiate the configuration definitions */
|
||||
#include "cpuRegisters.h"
|
||||
#include "cpuFamRegisters.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "AdvancedApi.h"
|
||||
#include "heapManager.h"
|
||||
#include "CreateStruct.h"
|
||||
#include "cpuFeatures.h"
|
||||
#include "Table.h"
|
||||
#include "cpuEarlyInit.h"
|
||||
#include "cpuLateInit.h"
|
||||
#include "GnbInterface.h"
|
||||
|
||||
/* Instantiate all solution relevant data */
|
||||
#include <PlatformInstall.h>
|
||||
|
|
@ -1,57 +0,0 @@
|
|||
#*****************************************************************************
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
#*****************************************************************************
|
||||
|
||||
entries
|
||||
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
#392 3 r 0 unused
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
399 1 e 2 multi_core
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
445 1 e 1 iommu
|
||||
456 1 e 1 ECC_memory
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 amd_reserved
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 5 Notice
|
||||
6 6 Info
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
8 0 400Mhz
|
||||
8 1 333Mhz
|
||||
8 2 266Mhz
|
||||
8 3 200Mhz
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,90 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
|
||||
u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
|
||||
u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
|
||||
u8 slot, u8 rfu)
|
||||
{
|
||||
pirq_info->bus = bus;
|
||||
pirq_info->devfn = devfn;
|
||||
pirq_info->irq[0].link = link0;
|
||||
pirq_info->irq[0].bitmap = bitmap0;
|
||||
pirq_info->irq[1].link = link1;
|
||||
pirq_info->irq[1].bitmap = bitmap1;
|
||||
pirq_info->irq[2].link = link2;
|
||||
pirq_info->irq[2].bitmap = bitmap2;
|
||||
pirq_info->irq[3].link = link3;
|
||||
pirq_info->irq[3].bitmap = bitmap3;
|
||||
pirq_info->slot = slot;
|
||||
pirq_info->rfu = rfu;
|
||||
}
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
|
||||
struct irq_routing_table *pirq;
|
||||
struct irq_info *pirq_info;
|
||||
u32 slot_num;
|
||||
u8 *v;
|
||||
|
||||
u8 sum = 0;
|
||||
int i;
|
||||
|
||||
/* Align the table to be 16 byte aligned. */
|
||||
addr += 15;
|
||||
addr &= ~15;
|
||||
|
||||
/* This table must be between 0xf0000 & 0x100000 */
|
||||
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
|
||||
|
||||
pirq = (void *)(addr);
|
||||
v = (u8 *) (addr);
|
||||
|
||||
pirq->signature = PIRQ_SIGNATURE;
|
||||
pirq->version = PIRQ_VERSION;
|
||||
|
||||
pirq->rtr_bus = 0;
|
||||
pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
|
||||
|
||||
pirq->exclusive_irqs = 0;
|
||||
|
||||
pirq->rtr_vendor = 0x1002;
|
||||
pirq->rtr_device = 0x4384;
|
||||
|
||||
pirq->miniport_data = 0;
|
||||
|
||||
memset(pirq->rfu, 0, sizeof(pirq->rfu));
|
||||
|
||||
pirq_info = (void *)(&pirq->checksum + 1);
|
||||
slot_num = 0;
|
||||
|
||||
/* pci bridge */
|
||||
write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
|
||||
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
|
||||
0);
|
||||
pirq_info++;
|
||||
|
||||
slot_num++;
|
||||
|
||||
pirq->size = 32 + 16 * slot_num;
|
||||
|
||||
for (i = 0; i < pirq->size; i++)
|
||||
sum += v[i];
|
||||
|
||||
sum = pirq->checksum - sum;
|
||||
|
||||
if (sum != pirq->checksum) {
|
||||
pirq->checksum = sum;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "%s done.\n", __func__);
|
||||
|
||||
return (unsigned long)pirq_info;
|
||||
|
||||
}
|
||||
|
|
@ -1,131 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
#include <southbridge/amd/cimx/sb800/SBPLATFORM.h>
|
||||
|
||||
u8 intr_data[] = {
|
||||
[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */
|
||||
[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */
|
||||
[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x10,0x11,0x12,0x13
|
||||
};
|
||||
|
||||
static void *smp_write_config_table(void *v)
|
||||
{
|
||||
struct mp_config_table *mc;
|
||||
int bus_isa;
|
||||
|
||||
/*
|
||||
* By the time this function gets called, the IOAPIC registers
|
||||
* have been written so they can be read to get the correct
|
||||
* APIC ID and Version
|
||||
*/
|
||||
u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
|
||||
u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
|
||||
mptable_init(mc, LOCAL_APIC_ADDR);
|
||||
memcpy(mc->mpc_oem, "AMD ", 8);
|
||||
|
||||
smp_write_processors(mc);
|
||||
|
||||
mptable_write_buses(mc, NULL, &bus_isa);
|
||||
|
||||
/* I/O APICs: APIC ID Version State Address */
|
||||
smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
|
||||
|
||||
u8 byte;
|
||||
|
||||
for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
|
||||
outb(byte | 0x80, 0xC00);
|
||||
outb(intr_data[byte], 0xC01);
|
||||
}
|
||||
|
||||
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
#define IO_LOCAL_INT(type, intr, apicid, pin) \
|
||||
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
|
||||
|
||||
mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
|
||||
|
||||
/* PCI interrupts are level triggered, and are
|
||||
* associated with a specific bus/device/function tuple.
|
||||
*/
|
||||
#define PCI_INT(bus, dev, fn, pin) \
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
|
||||
|
||||
/* APU Internal Graphic Device*/
|
||||
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
|
||||
PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
|
||||
|
||||
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
|
||||
PCI_INT(0x0, 0x14, 0x0, 0x10);
|
||||
/* Southbridge HD Audio: */
|
||||
PCI_INT(0x0, 0x14, 0x2, 0x12);
|
||||
|
||||
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
|
||||
PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
|
||||
PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
|
||||
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
|
||||
PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
|
||||
PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
|
||||
|
||||
/* sata */
|
||||
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
|
||||
|
||||
/* on board NIC & Slot PCIE. */
|
||||
|
||||
/* PCI slots */
|
||||
struct device *dev = pcidev_on_root(0x14, 4);
|
||||
if (dev && dev->enabled) {
|
||||
u8 bus_pci = dev->link_list->secondary;
|
||||
/* PCI_SLOT 0. */
|
||||
PCI_INT(bus_pci, 0x5, 0x0, 0x14);
|
||||
PCI_INT(bus_pci, 0x5, 0x1, 0x15);
|
||||
PCI_INT(bus_pci, 0x5, 0x2, 0x16);
|
||||
PCI_INT(bus_pci, 0x5, 0x3, 0x17);
|
||||
|
||||
/* PCI_SLOT 1. */
|
||||
PCI_INT(bus_pci, 0x6, 0x0, 0x15);
|
||||
PCI_INT(bus_pci, 0x6, 0x1, 0x16);
|
||||
PCI_INT(bus_pci, 0x6, 0x2, 0x17);
|
||||
PCI_INT(bus_pci, 0x6, 0x3, 0x14);
|
||||
|
||||
/* PCI_SLOT 2. */
|
||||
PCI_INT(bus_pci, 0x7, 0x0, 0x16);
|
||||
PCI_INT(bus_pci, 0x7, 0x1, 0x17);
|
||||
PCI_INT(bus_pci, 0x7, 0x2, 0x14);
|
||||
PCI_INT(bus_pci, 0x7, 0x3, 0x15);
|
||||
}
|
||||
|
||||
/* PCIe PortA */
|
||||
PCI_INT(0x0, 0x15, 0x0, 0x10);
|
||||
/* PCIe PortB */
|
||||
PCI_INT(0x0, 0x15, 0x1, 0x11);
|
||||
/* PCIe PortC */
|
||||
PCI_INT(0x0, 0x15, 0x2, 0x12);
|
||||
/* PCIe PortD */
|
||||
PCI_INT(0x0, 0x15, 0x3, 0x13);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
|
||||
IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
return mptable_finalize(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr, 0);
|
||||
return (unsigned long)smp_write_config_table(v);
|
||||
}
|
||||
|
|
@ -1,229 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
|
||||
#ifndef _PLATFORM_CFG_H_
|
||||
#define _PLATFORM_CFG_H_
|
||||
|
||||
/**
|
||||
* @def BIOS_SIZE
|
||||
* BIOS_SIZE_{1,2,4,8,16}M
|
||||
*
|
||||
* In SB800, default ROM size is 1M Bytes, if your platform ROM
|
||||
* bigger than 1M you have to set the ROM size outside CIMx module and
|
||||
* before AGESA module get call.
|
||||
*/
|
||||
#ifndef BIOS_SIZE
|
||||
#define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1)
|
||||
#endif /* BIOS_SIZE */
|
||||
|
||||
/**
|
||||
* @def SPREAD_SPECTRUM
|
||||
* @brief
|
||||
* 0 - Disable Spread Spectrum function
|
||||
* 1 - Enable Spread Spectrum function
|
||||
*/
|
||||
#define SPREAD_SPECTRUM 0
|
||||
|
||||
/**
|
||||
* @def SB_HPET_TIMER
|
||||
* @brief
|
||||
* 0 - Disable hpet
|
||||
* 1 - Enable hpet
|
||||
*/
|
||||
#define HPET_TIMER 1
|
||||
|
||||
/**
|
||||
* @def USB_CONFIG
|
||||
* @brief bit[0-6] used to control USB
|
||||
* 0 - Disable
|
||||
* 1 - Enable
|
||||
* Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0
|
||||
* Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1
|
||||
* Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2
|
||||
* Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3
|
||||
* Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4
|
||||
* Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5
|
||||
* Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6
|
||||
*/
|
||||
#define USB_CONFIG 0x0F
|
||||
|
||||
/**
|
||||
* @def PCI_CLOCK_CTRL
|
||||
* @brief bit[0-4] used for PCI Slots Clock Control,
|
||||
* 0 - disable
|
||||
* 1 - enable
|
||||
* PCI SLOT 0 define at BIT0
|
||||
* PCI SLOT 1 define at BIT1
|
||||
* PCI SLOT 2 define at BIT2
|
||||
* PCI SLOT 3 define at BIT3
|
||||
* PCI SLOT 4 define at BIT4
|
||||
*/
|
||||
#define PCI_CLOCK_CTRL 0x1E
|
||||
|
||||
/**
|
||||
* @def SATA_CONTROLLER
|
||||
* @brief INCHIP Sata Controller
|
||||
*/
|
||||
#define SATA_CONTROLLER CIMX_OPTION_ENABLED
|
||||
|
||||
/**
|
||||
* @def SATA_MODE
|
||||
* @brief INCHIP Sata Controller Mode
|
||||
* NOTE: DO NOT ALLOW SATA & IDE use same mode
|
||||
*/
|
||||
#define SATA_MODE CONFIG_SB800_SATA_MODE
|
||||
|
||||
/**
|
||||
* @brief INCHIP Sata IDE Controller Mode
|
||||
*/
|
||||
#define IDE_LEGACY_MODE 0
|
||||
#define IDE_NATIVE_MODE 1
|
||||
|
||||
/**
|
||||
* @def SATA_IDE_MODE
|
||||
* @brief INCHIP Sata IDE Controller Mode
|
||||
* NOTE: DO NOT ALLOW SATA & IDE use same mode
|
||||
*/
|
||||
#define SATA_IDE_MODE IDE_LEGACY_MODE
|
||||
|
||||
/**
|
||||
* @def EXTERNAL_CLOCK
|
||||
* @brief 00/10: Reference clock from crystal oscillator via
|
||||
* PAD_XTALI and PAD_XTALO
|
||||
*
|
||||
* @def INTERNAL_CLOCK
|
||||
* @brief 01/11: Reference clock from internal clock through
|
||||
* CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
|
||||
*/
|
||||
#define EXTERNAL_CLOCK 0x00
|
||||
#define INTERNAL_CLOCK 0x01
|
||||
|
||||
/* NOTE: inagua have to using internal clock,
|
||||
* otherwise can not detect sata drive
|
||||
*/
|
||||
#define SATA_CLOCK_SOURCE INTERNAL_CLOCK
|
||||
|
||||
/**
|
||||
* @def SATA_PORT_MULT_CAP_RESERVED
|
||||
* @brief 1 ON, 0 0FF
|
||||
*/
|
||||
#define SATA_PORT_MULT_CAP_RESERVED 1
|
||||
|
||||
|
||||
/**
|
||||
* @def AZALIA_AUTO
|
||||
* @brief Detect Azalia controller automatically.
|
||||
*
|
||||
* @def AZALIA_DISABLE
|
||||
* @brief Disable Azalia controller.
|
||||
|
||||
* @def AZALIA_ENABLE
|
||||
* @brief Enable Azalia controller.
|
||||
*/
|
||||
#define AZALIA_AUTO 0
|
||||
#define AZALIA_DISABLE 1
|
||||
#define AZALIA_ENABLE 2
|
||||
|
||||
/**
|
||||
* @brief INCHIP HDA controller
|
||||
*/
|
||||
#define AZALIA_CONTROLLER AZALIA_AUTO
|
||||
|
||||
/**
|
||||
* @def AZALIA_PIN_CONFIG
|
||||
* @brief
|
||||
* 0 - disable
|
||||
* 1 - enable
|
||||
*/
|
||||
#define AZALIA_PIN_CONFIG 1
|
||||
|
||||
/**
|
||||
* @def AZALIA_SDIN_PIN
|
||||
* @brief
|
||||
* SDIN0 is define at BIT0 & BIT1
|
||||
* 00 - GPIO PIN
|
||||
* 01 - Reserved
|
||||
* 10 - As a Azalia SDIN pin
|
||||
* SDIN1 is define at BIT2 & BIT3
|
||||
* SDIN2 is define at BIT4 & BIT5
|
||||
* SDIN3 is define at BIT6 & BIT7
|
||||
*/
|
||||
#define AZALIA_SDIN_PIN 0x2A
|
||||
|
||||
/**
|
||||
* @def GPP_CONTROLLER
|
||||
*/
|
||||
#define GPP_CONTROLLER CIMX_OPTION_ENABLED
|
||||
|
||||
/**
|
||||
* @def GPP_CFGMODE
|
||||
* @brief GPP Link Configuration
|
||||
* four possible configuration:
|
||||
* GPP_CFGMODE_X4000
|
||||
* GPP_CFGMODE_X2200
|
||||
* GPP_CFGMODE_X2110
|
||||
* GPP_CFGMODE_X1111
|
||||
*/
|
||||
#define GPP_CFGMODE GPP_CFGMODE_X1111
|
||||
|
||||
/**
|
||||
* @def NB_SB_GEN2
|
||||
* 0 - Disable
|
||||
* 1 - Enable
|
||||
*/
|
||||
#define NB_SB_GEN2 TRUE
|
||||
|
||||
/**
|
||||
* @def SB_GPP_GEN2
|
||||
* 0 - Disable
|
||||
* 1 - Enable
|
||||
*/
|
||||
#define SB_GPP_GEN2 TRUE
|
||||
|
||||
/**
|
||||
* @def SB_GPP_UNHIDE_PORTS
|
||||
* TRUE - ports visible always, even port empty
|
||||
* FALSE - ports invisible if port empty
|
||||
*/
|
||||
#define SB_GPP_UNHIDE_PORTS FALSE
|
||||
|
||||
/**
|
||||
* @def GEC_CONFIG
|
||||
* 0 - Enable
|
||||
* 1 - Disable
|
||||
*/
|
||||
#define GEC_CONFIG 1
|
||||
|
||||
static const CODECENTRY sample_codec_alc886[] = /* Realtek ALC886/8 */
|
||||
{
|
||||
/* NID, PinConfig (Verbs 71F..C) */
|
||||
{0x11, 0x411111F0}, /* NPC */
|
||||
{0x12, 0x411111F0}, /* DMIC */
|
||||
{0x14, 0x01214110}, /* FRONT (Port-D) */
|
||||
{0x15, 0x01011112}, /* SURR (Port-A) */
|
||||
{0x16, 0x01016111}, /* CEN/LFE (Port-G) */
|
||||
{0x17, 0x411111F0}, /* SIDESURR (Port-H) */
|
||||
{0x18, 0x01A19930}, /* MIC1 (Port-B) */
|
||||
{0x19, 0x411111F0}, /* MIC2 (Port-F) */
|
||||
{0x1A, 0x0181313F}, /* LINE1 (Port-C) */
|
||||
{0x1B, 0x411111F0}, /* LINE2 (Port-E) */
|
||||
{0x1C, 0x411111F0}, /* CD-IN */
|
||||
{0x1D, 0x40132601}, /* BEEP-IN */
|
||||
{0x1E, 0x01441120}, /* S/PDIF-OUT */
|
||||
{0x1F, 0x01C46140}, /* S/PDIF-IN */
|
||||
{0xff, 0xffffffff} /* end of table */
|
||||
};
|
||||
|
||||
static const CODECTBLLIST codec_tablelist[] =
|
||||
{
|
||||
{0x10ec0888, (CODECENTRY*)&sample_codec_alc886[0]},
|
||||
{0xFFFFFFFF, (CODECENTRY*)0xFFFFFFFFL}
|
||||
};
|
||||
|
||||
/**
|
||||
* @def AZALIA_OEM_VERB_TABLE
|
||||
* Mainboard specific codec verb table list
|
||||
*/
|
||||
#define AZALIA_OEM_VERB_TABLE (&codec_tablelist[0])
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue