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sb/intel/i82801jx: Drop `c3_latency` 

The three mainboards using this southbridge do not define it. Note that
the default value of zero might be wrong, so add a FIXME comment.

Change-Id: Id16bb12a4628daf311bddf7e4701fc480d6b18e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2020-06-21 16:18:27 +02:00
parent 4cdc698707
commit 27387c3cf5
2 changed files with 1 additions and 2 deletions
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1
src/southbridge/intel/i82801jx/chip.h
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@ -48,7 +48,6 @@ struct southbridge_intel_i82801jx_config {
int c4onc3_enable:1;
int c5_enable : 1;
int c6_enable : 1;
int c3_latency;
int docking_supported:1;
int throttle_duty : 3;

2
src/southbridge/intel/i82801jx/fadt.c
View File

@ -36,7 +36,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = chip->c3_latency;
fadt->p_lvl3_lat = 0; /* FIXME: Is this correct? */
fadt->duty_offset = 1;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;