soc/intel/cnl: Use the common code to set the PchPmPwrCycDur
This patch uses the common code to avoid violating the PCH EDS recommendation for the PchPmPwrCycDur setting. Change-Id: Id418480bc779d56ff5586516d9bd99ca15133203 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45029 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
V Sowmya
Patrick Georgi
parent
d8a722cb61
commit
27413d3219
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@ -8,6 +8,7 @@
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#include <fsp/util.h>
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#include <intelblocks/lpss.h>
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#include <intelblocks/power_limit.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/xdci.h>
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#include <intelpch/lockdown.h>
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#include <soc/intel/common/vbt.h>
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@ -32,39 +33,6 @@ static const pci_devfn_t serial_io_dev[] = {
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PCH_DEVFN_UART2
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};
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/* List of Minimum Assertion durations in microseconds */
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enum min_assrt_dur {
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MinAssrtDur0s = 0,
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MinAssrtDur60us = 60,
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MinAssrtDur1ms = 1000,
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MinAssrtDur50ms = 50000,
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MinAssrtDur98ms = 98000,
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MinAssrtDur500ms = 500000,
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MinAssrtDur1s = 1000000,
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MinAssrtDur2s = 2000000,
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MinAssrtDur3s = 3000000,
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MinAssrtDur4s = 4000000,
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};
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/* Signal Assertion duration values */
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struct cfg_assrt_dur {
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/* Minimum assertion duration of SLP_A signal */
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enum min_assrt_dur slp_a;
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/* Minimum assertion duration of SLP_4 signal */
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enum min_assrt_dur slp_s4;
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/* Minimum assertion duration of SLP_3 signal */
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enum min_assrt_dur slp_s3;
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/* PCH PM Power Cycle duration */
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enum min_assrt_dur pm_pwr_cyc_dur;
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};
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/* Default value of PchPmPwrCycDur */
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#define PCH_PM_PWR_CYC_DUR 4
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/*
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* Given an enum for PCH_SERIAL_IO_MODE, 1 needs to be subtracted to get the FSP
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* UPD expected value for Serial IO since valid enum index starts from 1.
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@ -90,93 +58,6 @@ static uint8_t get_param_value(const config_t *config, uint32_t dev_offset)
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}
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#if CONFIG(SOC_INTEL_COMETLAKE)
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static enum min_assrt_dur get_high_asst_width(const struct cfg_assrt_dur *cfg_assrt_dur)
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{
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enum min_assrt_dur max_assert_dur = cfg_assrt_dur->slp_s4;
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if (max_assert_dur < cfg_assrt_dur->slp_s3)
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max_assert_dur = cfg_assrt_dur->slp_s3;
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if (max_assert_dur < cfg_assrt_dur->slp_a)
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max_assert_dur = cfg_assrt_dur->slp_a;
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return max_assert_dur;
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}
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static void get_min_assrt_dur(uint8_t slp_s4_min_asst, uint8_t slp_s3_min_asst,
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uint8_t slp_a_min_asst, uint8_t pm_pwr_cyc_dur,
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struct cfg_assrt_dur *cfg_assrt_dur)
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{
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/*
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* Ensure slp_x_dur_list[] elements are in sync with devicetree config to FSP encoded
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* values.
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* slp_s4_asst_dur_list : 1s, 1s, 2s, 3s, 4s(Default)
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*/
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const enum min_assrt_dur slp_s4_asst_dur_list[] = {
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MinAssrtDur1s, MinAssrtDur1s, MinAssrtDur2s, MinAssrtDur3s, MinAssrtDur4s
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};
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/* slp_s3_asst_dur_list: 50ms, 60us, 50ms (Default), 2s */
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const enum min_assrt_dur slp_s3_asst_dur_list[] = {
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MinAssrtDur50ms, MinAssrtDur60us, MinAssrtDur50ms, MinAssrtDur2s
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};
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/* slp_a_asst_dur_list: 2s, 0s, 4s, 98ms, 2s(Default) */
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const enum min_assrt_dur slp_a_asst_dur_list[] = {
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MinAssrtDur2s, MinAssrtDur0s, MinAssrtDur4s, MinAssrtDur98ms, MinAssrtDur2s
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};
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/* pm_pwr_cyc_dur_list: 4s(Default), 1s, 2s, 3s, 4s */
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const enum min_assrt_dur pm_pwr_cyc_dur_list[] = {
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MinAssrtDur4s, MinAssrtDur1s, MinAssrtDur2s, MinAssrtDur3s, MinAssrtDur4s
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};
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/* Get signal assertion width */
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if (slp_s4_min_asst < ARRAY_SIZE(slp_s4_asst_dur_list))
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cfg_assrt_dur->slp_s4 = slp_s4_asst_dur_list[slp_s4_min_asst];
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if (slp_s3_min_asst < ARRAY_SIZE(slp_s3_asst_dur_list))
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cfg_assrt_dur->slp_s3 = slp_s3_asst_dur_list[slp_s3_min_asst];
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if (slp_a_min_asst < ARRAY_SIZE(slp_a_asst_dur_list))
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cfg_assrt_dur->slp_a = slp_a_asst_dur_list[slp_a_min_asst];
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if (pm_pwr_cyc_dur < ARRAY_SIZE(pm_pwr_cyc_dur_list))
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cfg_assrt_dur->pm_pwr_cyc_dur = pm_pwr_cyc_dur_list[pm_pwr_cyc_dur];
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}
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static uint8_t get_pm_pwr_cyc_dur(uint8_t slp_s4_min_asst, uint8_t slp_s3_min_asst,
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uint8_t slp_a_min_asst, uint8_t pm_pwr_cyc_dur)
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{
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/* Sets default minimum asserton duration values */
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struct cfg_assrt_dur cfg_assrt_dur = {
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.slp_a = MinAssrtDur2s,
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.slp_s4 = MinAssrtDur4s,
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.slp_s3 = MinAssrtDur50ms,
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.pm_pwr_cyc_dur = MinAssrtDur4s
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};
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enum min_assrt_dur high_asst_width;
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/* Convert assertion durations from register-encoded to microseconds */
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get_min_assrt_dur(slp_s4_min_asst, slp_s3_min_asst, slp_a_min_asst, pm_pwr_cyc_dur,
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&cfg_assrt_dur);
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/* Get the higher assertion duration among PCH EDS specified signals for pwr_cyc_dur */
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high_asst_width = get_high_asst_width(&cfg_assrt_dur);
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if (cfg_assrt_dur.pm_pwr_cyc_dur >= high_asst_width)
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return pm_pwr_cyc_dur;
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printk(BIOS_DEBUG,
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"Set PmPwrCycDur to 4s as configured PmPwrCycDur(%d) violates PCH EDS "
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"spec\n", pm_pwr_cyc_dur);
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return PCH_PM_PWR_CYC_DUR;
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}
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static void parse_devicetree_param(const config_t *config, FSP_S_CONFIG *params)
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{
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uint32_t dev_offset = 0;
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