From 274d20a0652f45ed54834524c485f7ab59bcdf70 Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Sun, 15 May 2016 13:52:36 -0700 Subject: [PATCH] mainboard/intel/galileo: Add GPIO initialization Add Kconfig to configure coreboot for a specific Galileo board. Configure the GPIOs for the specific Galileo board. TEST=Build and run on Galileo Gen2 Change-Id: I992460d506b5543915c27f6a531da4b1a53d6505 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/14826 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/intel/galileo/Kconfig | 9 ++++ src/mainboard/intel/galileo/Makefile.inc | 2 + src/mainboard/intel/galileo/gen1.h | 53 ++++++++++++++++++++++++ src/mainboard/intel/galileo/gen2.h | 50 ++++++++++++++++++++++ src/mainboard/intel/galileo/gpio.c | 33 +++++++++++++++ 5 files changed, 147 insertions(+) create mode 100644 src/mainboard/intel/galileo/gen1.h create mode 100644 src/mainboard/intel/galileo/gen2.h create mode 100644 src/mainboard/intel/galileo/gpio.c diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index f89232fa49..6381ae82ba 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -34,4 +34,13 @@ config MAINBOARD_VENDOR string default "Intel" +config GALILEO_GEN2 + bool "Board generation: GEN1 (n) or GEN2 (y)" + default y + help + The coreboot binary will configure only one generation of the Galileo + board since coreboot can not determine the board generation at + runtime. Select which generation of the Galileo that coreboot + should initialize. + endif # BOARD_INTEL_QUARK diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 3ffba1c963..382f8b99fb 100644 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -14,3 +14,5 @@ ## CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark + +romstage-y += gpio.c diff --git a/src/mainboard/intel/galileo/gen1.h b/src/mainboard/intel/galileo/gen1.h new file mode 100644 index 0000000000..c718b617a8 --- /dev/null +++ b/src/mainboard/intel/galileo/gen1.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +static const struct reg_script gen1_gpio_init[] = { + /* Initialize the legacy GPIO controller */ + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGEN_CORE_WELL, 0x03), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGIO_CORE_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGLVL_CORE_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTPE_CORE_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTNE_CORE_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGGPE_CORE_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGSMI_CORE_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTS_CORE_WELL, 0x03), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CNMIEN_CORE_WELL, 0x00), + + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGEN_RESUME_WELL, 0x3f), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGIO_RESUME_WELL, 0x21), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGLVL_RESUME_WELL, 0x14), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTPE_RESUME_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTNE_RESUME_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGGPE_RESUME_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGSMI_RESUME_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTS_RESUME_WELL, 0x3f), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RNMIEN_RESUME_WELL, 0x00), + + /* Initialize the GPIO controller */ + REG_GPIO_WRITE(GPIO_INTEN, 0), + REG_GPIO_WRITE(GPIO_INTSTATUS, 0), + REG_GPIO_WRITE(GPIO_SWPORTA_DR, 5), + REG_GPIO_WRITE(GPIO_SWPORTA_DDR, 0x15), + REG_GPIO_WRITE(GPIO_INTMASK, 0), + REG_GPIO_WRITE(GPIO_INTTYPE_LEVEL, 0), + REG_GPIO_WRITE(GPIO_INT_POLARITY, 0), + REG_GPIO_WRITE(GPIO_DEBOUNCE, 0), + REG_GPIO_WRITE(GPIO_LS_SYNC, 0), + + /* Toggle the Cypress reset line */ + REG_GPIO_OR(GPIO_SWPORTA_DR, BIT4), + REG_GPIO_AND(GPIO_SWPORTA_DR, ~BIT4), + REG_SCRIPT_END +}; diff --git a/src/mainboard/intel/galileo/gen2.h b/src/mainboard/intel/galileo/gen2.h new file mode 100644 index 0000000000..dc8b6f5d6f --- /dev/null +++ b/src/mainboard/intel/galileo/gen2.h @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +static const struct reg_script gen2_gpio_init[] = { + /* Initialize the legacy GPIO controller */ + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGEN_CORE_WELL, 0x03), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGIO_CORE_WELL, 0x03), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGLVL_CORE_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTPE_CORE_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTNE_CORE_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGGPE_CORE_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGSMI_CORE_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTS_CORE_WELL, 0x03), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CNMIEN_CORE_WELL, 0x00), + + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGEN_RESUME_WELL, 0x3f), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGIO_RESUME_WELL, 0x1c), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGLVL_RESUME_WELL, 0x02), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTPE_RESUME_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTNE_RESUME_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGGPE_RESUME_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGSMI_RESUME_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTS_RESUME_WELL, 0x3f), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RNMIEN_RESUME_WELL, 0x00), + + /* Initialize the GPIO controller */ + REG_GPIO_WRITE(GPIO_INTEN, 0), + REG_GPIO_WRITE(GPIO_INTSTATUS, 0), + REG_GPIO_WRITE(GPIO_SWPORTA_DR, 5), + REG_GPIO_WRITE(GPIO_SWPORTA_DDR, 5), + REG_GPIO_WRITE(GPIO_INTMASK, 0), + REG_GPIO_WRITE(GPIO_INTTYPE_LEVEL, 0), + REG_GPIO_WRITE(GPIO_INT_POLARITY, 0), + REG_GPIO_WRITE(GPIO_DEBOUNCE, 0), + REG_GPIO_WRITE(GPIO_LS_SYNC, 0), + + REG_SCRIPT_END +}; diff --git a/src/mainboard/intel/galileo/gpio.c b/src/mainboard/intel/galileo/gpio.c new file mode 100644 index 0000000000..00b42403d1 --- /dev/null +++ b/src/mainboard/intel/galileo/gpio.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include "gen1.h" +#include "gen2.h" + +void mainboard_gpio_init(void) +{ + const struct reg_script *script; + + /* Initialize the GPIO controllers */ + if (IS_ENABLED(CONFIG_GALILEO_GEN2)) + script = gen2_gpio_init; + else + script = gen1_gpio_init; + reg_script_run(script); +}