src/northbridge: Remove unneeded include <arch/io.h>

Change-Id: I52ace93ae6f802723823955ac349ed54dc064aaa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

src/northbridge/intel/gm45/early_reset.c

@@ -15,7 +15,6 @@
  */
 
 #include <types.h>
-#include <arch/io.h>
 #include <cf9_reset.h>
 #include <device/pci_ops.h>
 

src/northbridge/intel/gm45/romstage.c

@@ -18,7 +18,6 @@
 #include <cbmem.h>
 #include <romstage_handoff.h>
 #include <console/console.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <arch/acpi.h>
 #include <cpu/x86/lapic.h>

src/northbridge/intel/haswell/raminit.c

@@ -15,7 +15,6 @@
 
 #include <console/console.h>
 #include <string.h>
-#include <arch/io.h>
 #include <cbmem.h>
 #include <arch/cbfs.h>
 #include <cbfs.h>

src/northbridge/intel/i945/raminit.c

@@ -18,7 +18,6 @@
 #include <cpu/x86/cache.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
-#include <arch/io.h>
 #include <cf9_reset.h>
 #include <device/mmio.h>
 #include <device/device.h>

src/northbridge/intel/pineview/raminit.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <cf9_reset.h>
 #include <device/mmio.h>
 #include <device/pci_ops.h>

src/northbridge/intel/pineview/romstage.c

@@ -17,7 +17,6 @@
  * so this one is named with prefix mainboard.
  */
 
-#include <arch/io.h>
 #include <timestamp.h>
 #include <console/console.h>
 #include <device/pci_ops.h>

src/northbridge/intel/sandybridge/raminit.c

@@ -21,7 +21,6 @@
 #include <cf9_reset.h>
 #include <string.h>
 #include <arch/cpu.h>
-#include <arch/io.h>
 #include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <cbmem.h>

src/northbridge/intel/sandybridge/raminit_mrc.c

@@ -18,7 +18,6 @@
 #include <bootmode.h>
 #include <cf9_reset.h>
 #include <string.h>
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <arch/cpu.h>
 #include <cbmem.h>

src/northbridge/intel/sandybridge/romstage.c

@@ -17,7 +17,6 @@
 
 #include <stdint.h>
 #include <console/console.h>
-#include <arch/io.h>
 #include <cf9_reset.h>
 #include <device/pci_ops.h>
 #include <cpu/x86/lapic.h>

src/northbridge/intel/x4x/raminit.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/io.h>
 #include <device/pci_ops.h>
 #include <cbmem.h>
 #include <cf9_reset.h>