Use common GCD function
Change-Id: I30e4b02a9ca6a15c9bc4edcf4143ffa13a21a732 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78799 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
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@ -1,6 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <commonlib/bsd/gcd.h>
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#include <delay.h>
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#include <device/i2c_simple.h>
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#include <edid.h>
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@ -152,30 +153,14 @@ static int wait_aux_op_finish(uint8_t bus)
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return 0;
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}
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static unsigned long gcd(unsigned long a, unsigned long b)
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{
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if (a == 0)
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return b;
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while (b != 0) {
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if (a > b)
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a = a - b;
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else
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b = b - a;
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}
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return a;
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}
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/* Reduce fraction a/b */
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static void anx7625_reduction_of_a_fraction(unsigned long *_a,
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unsigned long *_b)
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static void anx7625_reduction_of_a_fraction(u32 *_a, u32 *_b)
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{
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unsigned long gcd_num;
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unsigned long a = *_a, b = *_b, old_a, old_b;
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u32 gcd_num;
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u32 a = *_a, b = *_b, old_a, old_b;
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u32 denom = 1;
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gcd_num = gcd(a, b);
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gcd_num = gcd32(a, b);
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a /= gcd_num;
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b /= gcd_num;
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@ -198,9 +183,7 @@ static void anx7625_reduction_of_a_fraction(unsigned long *_a,
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*_b = b;
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}
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static int anx7625_calculate_m_n(u32 pixelclock,
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unsigned long *m, unsigned long *n,
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uint8_t *pd)
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static int anx7625_calculate_m_n(u32 pixelclock, u32 *m, u32 *n, uint8_t *pd)
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{
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uint8_t post_divider = *pd;
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if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) {
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@ -300,7 +283,7 @@ static int anx7625_odfc_config(uint8_t bus, uint8_t post_divider)
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static int anx7625_dsi_video_config(uint8_t bus, struct display_timing *dt)
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{
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unsigned long m, n;
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u32 m, n;
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u16 htotal;
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int ret;
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uint8_t post_divider = 0;
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@ -311,7 +294,7 @@ static int anx7625_dsi_video_config(uint8_t bus, struct display_timing *dt)
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return -1;
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}
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ANXINFO("compute M(%lu), N(%lu), divider(%d).\n", m, n, post_divider);
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ANXINFO("compute M(%u), N(%u), divider(%d).\n", m, n, post_divider);
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/* configure pixel clock */
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ret = anx7625_reg_write(bus, RX_P0_ADDR, PIXEL_CLOCK_L,
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@ -1,5 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <commonlib/bsd/gcd.h>
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#include <console/console.h>
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#include <cpu/intel/model_2065x/model_2065x.h>
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#include <cpu/x86/msr.h>
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@ -11,31 +12,14 @@
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#define NORTHBRIDGE PCI_DEV(0, 0, 0)
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static unsigned int gcd(unsigned int a, unsigned int b)
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{
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unsigned int t;
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if (a > b) {
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t = a;
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a = b;
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b = t;
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}
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/* invariant a < b. */
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while (a) {
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t = b % a;
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b = a;
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a = t;
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}
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return b;
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}
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static inline int div_roundup(int a, int b)
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{
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return DIV_ROUND_UP(a, b);
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}
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static unsigned int lcm(unsigned int a, unsigned int b)
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static u32 lcm(u32 a, u32 b)
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{
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return (a * b) / gcd(a, b);
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return (a * b) / gcd32(a, b);
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}
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struct stru1 {
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@ -65,7 +49,7 @@ compute_frequence_ratios(struct raminfo *info, u16 freq1, u16 freq2,
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int freq_max_reduced;
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int freq3, freq4;
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g = gcd(freq1, freq2);
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g = gcd32(freq1, freq2);
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freq1_reduced = freq1 / g;
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freq2_reduced = freq2 / g;
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freq_min_reduced = MIN(freq1_reduced, freq2_reduced);
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@ -1,9 +1,10 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/mmio.h>
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#include <assert.h>
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#include <commonlib/bsd/gcd.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/mmio.h>
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#include <lib.h>
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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@ -438,16 +439,6 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz)
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}
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}
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static u32 clk_gcd(u32 a, u32 b)
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{
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while (b != 0) {
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int r = b;
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b = a % b;
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a = r;
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}
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return a;
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}
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void rkclk_configure_i2s(unsigned int hz)
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{
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int n, d;
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@ -462,7 +453,7 @@ void rkclk_configure_i2s(unsigned int hz)
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1 << 15 | 0 << 12 | 1 << 8 | 0 << 0));
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/* set frac divider */
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v = clk_gcd(GPLL_HZ, hz);
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v = gcd32(GPLL_HZ, hz);
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n = (GPLL_HZ / v) & (0xffff);
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d = (hz / v) & (0xffff);
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assert(hz == GPLL_HZ / n * d);
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@ -1,9 +1,10 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <assert.h>
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#include <commonlib/bsd/gcd.h>
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#include <console/console.h>
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#include <device/mmio.h>
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#include <delay.h>
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#include <device/mmio.h>
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include <soc/grf.h>
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return freq;
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}
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static u32 clk_gcd(u32 a, u32 b)
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{
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while (b != 0) {
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int r = b;
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b = a % b;
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a = r;
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}
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return a;
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}
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void rkclk_configure_i2s(unsigned int hz)
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{
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int n, d;
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RK_CLRBITS(1 << 12 | 1 << 5 | 1 << 4 | 1 << 3));
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/* set frac divider */
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v = clk_gcd(CPLL_HZ, hz);
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v = gcd32(CPLL_HZ, hz);
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n = (CPLL_HZ / v) & (0xffff);
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d = (hz / v) & (0xffff);
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assert(hz == (u64)CPLL_HZ * d / n);
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