mb/google/brya: Remove Pcie Generic driver for WWAN
This was to merge PCIe ACPI code to WWAN device. But, now use recent _DSD generation changes in FM driver instead. PCie generic driver is not used for WWAN at this time. Also, RTD3 devices are moved to overridetree.cb where WWAN is present. BUG=b:221250331 BRANCH=firmware-brya-14505.B TEST= Check that _DSD is added to WWAN device in SSDT for the variants. Check that RTD3 is added to WWAN device in SSDT for the variants. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ia343c7545cf30bdbcd1de19e5eb84049dbb2977f Reviewed-on: https://review.coreboot.org/c/coreboot/+/62330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -15,7 +15,6 @@ config BOARD_GOOGLE_BRYA_COMMON
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select DRIVERS_INTEL_PMC
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select DRIVERS_INTEL_SOUNDWIRE
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select DRIVERS_INTEL_USB4_RETIMER
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select DRIVERS_PCIE_GENERIC
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select DRIVERS_SOUNDWIRE_ALC5682
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select DRIVERS_SOUNDWIRE_MAX98373
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select DRIVERS_SPI_ACPI
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@ -147,26 +147,6 @@ chip soc/intel/alderlake
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device ref i2c3 on end
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device ref heci1 on end
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device ref sata on end
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device ref pcie_rp6 on
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# Enable WWAN PCIE 6 using clk 5
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chip soc/intel/common/block/pcie/rtd3
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
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register "reset_off_delay_ms" = "20"
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register "srcclk_pin" = "5"
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register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
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register "skip_on_off_support" = "true"
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device generic 0 alias rp6_rtd3 on end
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end
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register "pch_pcie_rp[PCH_RP(6)]" = "{
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.clk_src = 5,
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.clk_req = 5,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip drivers/pcie/generic
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register "is_untrusted" = "1"
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device pci 0 on end
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end
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end #PCIE6 WWAN
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device ref pcie_rp8 on
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# Enable SD Card PCIE 8 using clk 3
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register "pch_pcie_rp[PCH_RP(8)]" = "{
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@ -189,7 +189,23 @@ chip soc/intel/alderlake
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end
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end
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device ref pcie_rp6 on
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probe DB_LTE LTE_PCIE
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# Enable WWAN PCIE 6 using clk 5
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register "pch_pcie_rp[PCH_RP(6)]" = "{
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.clk_src = 5,
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.clk_req = 5,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
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register "reset_off_delay_ms" = "20"
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# register "reset_delay_ms" = "1000"
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register "srcclk_pin" = "5"
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register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
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register "skip_on_off_support" = "true"
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device generic 0 alias rp6_rtd3 on
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probe DB_LTE LTE_PCIE
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end
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end
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chip drivers/wwan/fm
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register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
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@ -197,11 +213,11 @@ chip soc/intel/alderlake
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register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
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register "add_acpi_dma_property" = "true"
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use rp6_rtd3 as rtd3dev
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device generic 0 alias rp6_wwan on
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device generic 0 on
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probe DB_LTE LTE_PCIE
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end
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end
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probe DB_LTE LTE_PCIE
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end
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device ref tcss_dma0 on
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chip drivers/intel/usb4/retimer
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@ -188,7 +188,23 @@ chip soc/intel/alderlake
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end
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end
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device ref pcie_rp6 on
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probe DB_LTE LTE_PCIE
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# Enable WWAN PCIE 6 using clk 5
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register "pch_pcie_rp[PCH_RP(6)]" = "{
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.clk_src = 5,
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.clk_req = 5,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
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register "reset_off_delay_ms" = "20"
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# register "reset_delay_ms" = "1000"
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register "srcclk_pin" = "5"
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register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
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register "skip_on_off_support" = "true"
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device generic 0 alias rp6_rtd3 on
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probe DB_LTE LTE_PCIE
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end
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end
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chip drivers/wwan/fm
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register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
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@ -196,10 +212,11 @@ chip soc/intel/alderlake
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register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
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register "add_acpi_dma_property" = "true"
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use rp6_rtd3 as rtd3dev
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device generic 0 alias rp6_wwan on
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device generic 0 on
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probe DB_LTE LTE_PCIE
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end
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end
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probe DB_LTE LTE_PCIE
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end
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device ref tcss_dma0 on
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chip drivers/intel/usb4/retimer
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@ -174,7 +174,23 @@ chip soc/intel/alderlake
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end
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end
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device ref pcie_rp6 on
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probe DB_LTE LTE_PCIE
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# Enable WWAN PCIE 6 using clk 5
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register "pch_pcie_rp[PCH_RP(6)]" = "{
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.clk_src = 5,
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.clk_req = 5,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
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register "reset_off_delay_ms" = "20"
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# register "reset_delay_ms" = "1000"
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register "srcclk_pin" = "5"
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register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
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register "skip_on_off_support" = "true"
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device generic 0 alias rp6_rtd3 on
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probe DB_LTE LTE_PCIE
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end
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end
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chip drivers/wwan/fm
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register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
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@ -182,10 +198,11 @@ chip soc/intel/alderlake
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register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
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register "add_acpi_dma_property" = "true"
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use rp6_rtd3 as rtd3dev
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device generic 0 alias rp6_wwan on
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device generic 0 on
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probe DB_LTE LTE_PCIE
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end
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end
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probe DB_LTE LTE_PCIE
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end
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device ref tcss_dma0 on
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chip drivers/intel/usb4/retimer
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@ -160,7 +160,23 @@ chip soc/intel/alderlake
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end
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end
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device ref pcie_rp6 on
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probe DB_LTE LTE_PCIE
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# Enable WWAN PCIE 6 using clk 5
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register "pch_pcie_rp[PCH_RP(6)]" = "{
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.clk_src = 5,
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.clk_req = 5,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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chip soc/intel/common/block/pcie/rtd3
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
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register "reset_off_delay_ms" = "20"
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# register "reset_delay_ms" = "1000"
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register "srcclk_pin" = "5"
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register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
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register "skip_on_off_support" = "true"
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device generic 0 alias rp6_rtd3 on
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probe DB_LTE LTE_PCIE
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end
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end
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chip drivers/wwan/fm
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register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
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@ -168,10 +184,11 @@ chip soc/intel/alderlake
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register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
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register "add_acpi_dma_property" = "true"
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use rp6_rtd3 as rtd3dev
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device generic 0 alias rp6_wwan on
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device generic 0 on
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probe DB_LTE LTE_PCIE
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end
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end
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probe DB_LTE LTE_PCIE
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end
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device ref tcss_dma0 on
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chip drivers/intel/usb4/retimer
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