diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig
index a30cb7091b..2513c50030 100644
--- a/src/arch/riscv/Kconfig
+++ b/src/arch/riscv/Kconfig
@@ -2,6 +2,13 @@ config ARCH_RISCV
 	bool
 	default n
 
+config ARCH_RISCV_COMPRESSED
+	bool
+	default n
+	help
+	  Enable this option if your RISC-V processor supports compressed
+	  instructions (RVC). Currently, this enables RVC for all stages.
+
 config ARCH_BOOTBLOCK_RISCV
 	bool
 	default n
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index d2b6cce11d..4b2ff035d7 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -15,14 +15,24 @@
 ##
 ################################################################################
 
-riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany
-
-riscv_asm_flags =
+################################################################################
+## RISC-V specific options
+################################################################################
 
 ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)
 check-ramstage-overlap-regions += stack
 endif
 
+riscv_arch = rv64imafd
+
+ifeq ($(CONFIG_ARCH_RISCV_COMPRESSED),y)
+	riscv_arch := $(riscv_arch)c
+endif
+
+riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany -march=$(riscv_arch)
+
+riscv_asm_flags = -march=$(riscv_arch)
+
 ################################################################################
 ## bootblock
 ################################################################################