rockchip: Remove pulls for gpio_output(), clean up code

Output GPIOs should never have a pull-up or pull-down resistor attached
since they're actively driven. Since some GPIOs get initialized with a
pull at power-on reset, we should explicitly overwrite that setting.
Most other platforms do this on gpio_output, but Rockchip hadn't yet.

Also, shuffle some code around to make things cleaner and allow for
easier code reuse.

BRANCH=None
BUG=chrome-os-partner:52526
TEST=Booted Kevin.

Change-Id: I1425d074ea1e90f4484e1e84a8002b057192c5f7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: df5b236bfd58b172435043c1cb792b917a4ec4ab
Original-Change-Id: I044266d71ef8bd0518316ff72d829d1ca1e30f35
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/382531
Original-Reviewed-by: Simon Glass <sjg@google.com>
Reviewed-on: https://review.coreboot.org/16710
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/soc/rockchip/common/gpio.c

@@ -21,10 +21,15 @@
 #include <soc/soc.h>
 #include <stdlib.h>
 
-static void __gpio_input(gpio_t gpio, u32 pull)
+static void gpio_set_dir(gpio_t gpio, enum gpio_dir dir)
+{
+	clrsetbits_le32(&gpio_port[gpio.port]->swporta_ddr,
+			1 << gpio.num, dir << gpio.num);
+}
+
+static void gpio_set_pull(gpio_t gpio, enum gpio_pull pull)
 {
 	u32 pull_val = gpio_get_pull_val(gpio, pull);
-	clrbits_le32(&gpio_port[gpio.port]->swporta_ddr, 1 << gpio.num);
 	if (is_pmu_gpio(gpio))
 		clrsetbits_le32(gpio_grf_reg(gpio), 3 << (gpio.idx * 2),
 				pull_val << (gpio.idx * 2));
@@ -35,17 +40,20 @@ static void __gpio_input(gpio_t gpio, u32 pull)
 
 void gpio_input(gpio_t gpio)
 {
-	__gpio_input(gpio, PULLNONE);
+	gpio_set_pull(gpio, GPIO_PULLNONE);
+	gpio_set_dir(gpio, GPIO_INPUT);
 }
 
 void gpio_input_pulldown(gpio_t gpio)
 {
-	__gpio_input(gpio, PULLDOWN);
+	gpio_set_pull(gpio, GPIO_PULLDOWN);
+	gpio_set_dir(gpio, GPIO_INPUT);
 }
 
 void gpio_input_pullup(gpio_t gpio)
 {
-	__gpio_input(gpio, PULLUP);
+	gpio_set_pull(gpio, GPIO_PULLUP);
+	gpio_set_dir(gpio, GPIO_INPUT);
 }
 
 int gpio_get(gpio_t gpio)
@@ -55,7 +63,8 @@ int gpio_get(gpio_t gpio)
 
 void gpio_output(gpio_t gpio, int value)
 {
-	setbits_le32(&gpio_port[gpio.port]->swporta_ddr, 1 << gpio.num);
 	clrsetbits_le32(&gpio_port[gpio.port]->swporta_dr, 1 << gpio.num,
 							   !!value << gpio.num);
+	gpio_set_dir(gpio, GPIO_OUTPUT);
+	gpio_set_pull(gpio, GPIO_PULLNONE);
 }

src/soc/rockchip/common/include/soc/gpio.h

@@ -73,13 +73,18 @@ int is_pmu_gpio(gpio_t gpio);
 /* Return the io addr of gpio register */
 void *gpio_grf_reg(gpio_t gpio);
 
-enum {
+enum gpio_pull {
-	PULLNONE = 0,
+	GPIO_PULLNONE = 0,
-	PULLUP,
+	GPIO_PULLUP = 1,
-	PULLDOWN
+	GPIO_PULLDOWN = 2,
+};
+
+enum gpio_dir {
+	GPIO_INPUT = 0,
+	GPIO_OUTPUT = 1,
 };
 
 /* The gpio pull bias setting may be different between SoCs */
-u32 gpio_get_pull_val(gpio_t gpio, u32 pull);
+u32 gpio_get_pull_val(gpio_t gpio, enum gpio_pull pull);
 
 #endif

src/soc/rockchip/rk3288/gpio.c

@@ -51,7 +51,7 @@ void *gpio_grf_reg(gpio_t gpio)
 	return &rk3288_grf->gpio1_p[(gpio.port - 1)][gpio.bank];
 }
 
-u32 gpio_get_pull_val(gpio_t gpio, u32 pull)
+u32 gpio_get_pull_val(gpio_t gpio, enum gpio_pull pull)
 {
 	/* use the default gpio pull bias setting defined in soc/gpio.h */
 	return pull;

src/soc/rockchip/rk3399/gpio.c

@@ -56,7 +56,7 @@ enum {
 	PULLUP_1V8 = 3,
 };
 
-u32 gpio_get_pull_val(gpio_t gpio, u32 pull)
+u32 gpio_get_pull_val(gpio_t gpio, enum gpio_pull pull)
 {
 	/* The default pull bias setting defined in soc/gpio.h */
 	u32 pull_val = pull;
@@ -67,13 +67,13 @@ u32 gpio_get_pull_val(gpio_t gpio, u32 pull)
 	if (IS_GPIO_BANK(gpio, 0, A) || IS_GPIO_BANK(gpio, 0, B) ||
 	    IS_GPIO_BANK(gpio, 2, C) || IS_GPIO_BANK(gpio, 2, D)) {
 		switch (pull) {
-		case PULLUP:
+		case GPIO_PULLUP:
 			pull_val = PULLUP_1V8;
 			break;
-		case PULLDOWN:
+		case GPIO_PULLDOWN:
 			pull_val = PULLDOWN_1V8;
 			break;
-		default:
+		case GPIO_PULLNONE:
 			pull_val = PULLNONE_1V8;
 		}
 	}