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mb/google/zoombini/variants/meowth: Enable NVMe 

Turn on pcie ports 9,10. Enable Root Port 9 and set up clkreq 3.

BUG=b:72120814
TEST: Boot to OS via NVMe

Change-Id: I272b63b11e6b00ae5bdbef5a37ee517cc0636f6d
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/23208
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Bora Guvendik 2018-01-10 14:20:03 -08:00 committed by Martin Roth
parent d2517af6f9
commit 277f4b9974
1 changed files with 6 additions and 1 deletions
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7
src/mainboard/google/zoombini/variants/meowth/devicetree.cb
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@ -73,6 +73,11 @@ chip soc/intel/cannonlake
# Enable cpufreq
register "speed_shift_enable" = "1"
# Enable Root port 8 (PCIe port 9) for NVMe
register "PcieRpEnable[8]" = "1"
register "PcieClkSrcUsage[3]" = "8"
register "PcieClkSrcClkReq[3]" = "3"
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
@ -129,7 +134,7 @@ chip soc/intel/cannonlake
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 off end # PCI Express Port 9
device pci 1d.0 on end # PCI Express Port 9
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12