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purism/librem13: Add support for Purism Librem 13 mainboard 

This adds support for booting the Purism Librem 13 mainboard
with coreboot, using binaries extracted from the original BIOS
and from a Broadwell Chromebook.

The following features have been tested on Ubuntu 15.10:
- Input: Keyboard and Trackpad
- SATA: Internal HDD and M.2 NGFF
- Network: WiFi and Ethernet
- USB: Bluetooth, Camera, SD Card, Ports (1xUSB2 and 1xUSB3)
- Video: Internal panel and HDMI port
- Internal speakers and microphone (headphones do not work)
- EC handling for battery, AC, lid, special keys

These binaries are extracted from the original BIOS:
- VGA BIOS
- Management Engine
- Intel Firmware Descriptor

These binaries are extracted from a Broadwell Chromebook BIOS:
- MemoryInit reference code binary
- SiliconInit reference code binary

This was developed and tested on an Librem 13 device.  For those
who may want to do more development you can use EHCI debug and the
right USB port to get coreboot output.

Change-Id: Ia72e2d7ddc8ba5eef63819e5677122a5a5c705d8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/13026
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Duncan Laurie 2015-12-22 17:27:02 -08:00 committed by Martin Roth
parent 420b2a513e
commit 27807c66ee
18 changed files with 753 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
src/mainboard/purism/Kconfig Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2015 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if VENDOR_PURISM
choice
prompt "Mainboard model"
source "src/mainboard/purism/*/Kconfig.name"
endchoice
source "src/mainboard/purism/*/Kconfig"
config MAINBOARD_VENDOR
string "Mainboard Vendor"
default "Purism"
endif # VENDOR_PURISM

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src/mainboard/purism/Kconfig.name Normal file
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config VENDOR_PURISM
bool "Purism"

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src/mainboard/purism/librem13/Kconfig Normal file
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if BOARD_PURISM_LIBREM13
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select BOARD_ROMSIZE_KB_8192
select EC_PURISM_LIBEM
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_INT15
select SOC_INTEL_BROADWELL
config DRIVERS_PS2_KEYBOARD
def_bool y
help
Default PS/2 Keyboard to enabled on this board.
config DRIVERS_UART_8250IO
def_bool n
help
This platform does not have any way to get standard
serial output so disable it by default.
config HAVE_IFD_BIN
bool
default n
config HAVE_ME_BIN
bool
default n
config MAINBOARD_DIR
string
default purism/librem13
config MAINBOARD_PART_NUMBER
string
default "Librem 13"
config MAX_CPUS
int
default 8
config NO_POST
def_bool y
help
This platform does not have any way to see POST codes
so disable them by default.
config PRE_GRAPHICS_DELAY
int
default 50
config VGA_BIOS_ID
string
default "8086,1616"
endif

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src/mainboard/purism/librem13/Kconfig.name Normal file
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config BOARD_PURISM_LIBREM13
bool "Librem 13"

17
src/mainboard/purism/librem13/Makefile.inc Normal file
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##
## This file is part of the coreboot project.
##
## Copyright (C) 2016 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
romstage-y += pei_data.c
ramstage-y += pei_data.c

18
src/mainboard/purism/librem13/acpi/ec.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define EC_SCI_GPI 10
#include <ec/purism/librem/acpi/ec.asl>

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src/mainboard/purism/librem13/acpi/mainboard.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
Scope (\_SB)
{
Device (LID0)
{
Name (_HID, EisaId ("PNP0C0D"))
Method (_STA)
{
Return (0xF)
}
Method (_LID)
{
Return (\_SB.PCI0.LPCB.EC.LIDS)
}
}
Device (PWRB)
{
Name (_HID, EisaId ("PNP0C0C"))
Method (_STA)
{
Return (0xF)
}
Name (_PRW, Package () { 27, 4 })
}
Device (SLPB)
{
Name (_HID, EisaId ("PNP0C0E"))
Method (_STA)
{
Return (0xF)
}
}
}

16
src/mainboard/purism/librem13/acpi/superio.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <drivers/pc80/ps2_controller.asl>

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src/mainboard/purism/librem13/acpi_tables.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <arch/ioapic.h>
#include <soc/acpi.h>
#include <soc/nvs.h>
void acpi_create_gnvs(global_nvs_t *gnvs)
{
acpi_init_gnvs(gnvs);
}
unsigned long acpi_fill_madt(unsigned long current)
{
/* Local APICs */
current = acpi_create_madt_lapics(current);
/* IOAPIC */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
2, IO_APIC_ADDR, 0);
return acpi_madt_irq_overrides(current);
}

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src/mainboard/purism/librem13/board_info.txt Normal file
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Category: laptop
Vendor name: Purism
Board name: Librem 13
Board URL: https://puri.sm/librem-13/
ROM package: SOIC8
ROM protocol: SPI
ROM socketed: n
Flashrom support: y
Release year: 2015

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src/mainboard/purism/librem13/devicetree.cb Normal file
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chip soc/intel/broadwell
# Enable eDP Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
# Enable DDI1 Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
# Set backlight PWM values for eDP
register "gpu_cpu_backlight" = "0x00000200"
register "gpu_pch_backlight" = "0x04000200"
# Enable Panel and configure power delays
register "gpu_panel_port_select" = "1" # eDP
register "gpu_panel_power_cycle_delay" = "6" # 500ms
register "gpu_panel_power_up_delay" = "2000" # 200ms
register "gpu_panel_power_down_delay" = "500" # 50ms
register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms
register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
# Port 0 is HDD
# Port 3 is M.2 NGFF
register "sata_port_map" = "0x9"
# Port 0 tuning for link stability
register "sata_port0_gen3_dtle" = "9"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller
device pci 03.0 on end # mini-hd audio
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI
device pci 15.0 off end # Serial I/O DMA
device pci 15.1 off end # I2C0
device pci 15.2 off end # I2C1
device pci 15.3 off end # GSPI0
device pci 15.4 off end # GSPI1
device pci 15.5 off end # UART0
device pci 15.6 off end # UART1
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 17.0 off end # SDIO
device pci 19.0 off end # GbE
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 off end # PCIe Port #1
device pci 1c.1 off end # PCIe Port #2
device pci 1c.2 on end # PCIe Port #3 - LAN
device pci 1c.3 on end # PCIe Port #4 - WiFi
device pci 1c.4 off end # PCIe Port #5
device pci 1c.5 off end # PCIe Port #6
device pci 1d.0 off end # USB2 EHCI
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
chip ec/purism/librem
device pnp 0c09.0 on end
end
end # LPC bridge
device pci 1f.2 on end # SATA Controller
device pci 1f.3 on end # SMBus
device pci 1f.6 off end # Thermal
end
end

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src/mainboard/purism/librem13/dsdt.asl Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x05, /* DSDT revision: ACPI v5.0 */
"COREv4", /* OEM id */
"COREBOOT", /* OEM table id */
0x20160115 /* OEM revision */
)
{
/* Some generic macros */
#include <soc/intel/broadwell/acpi/platform.asl>
/* Global NVS and variables */
#include <soc/intel/broadwell/acpi/globalnvs.asl>
/* CPU */
#include <soc/intel/broadwell/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <soc/intel/broadwell/acpi/systemagent.asl>
#include <soc/intel/broadwell/acpi/pch.asl>
}
}
/* Chipset specific sleep states */
#include <soc/intel/broadwell/acpi/sleepstates.asl>
/* Mainboard specific */
#include "acpi/mainboard.asl"
}

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src/mainboard/purism/librem13/fadt.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <string.h>
#include <soc/acpi.h>
void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
{
acpi_header_t *header = &fadt->header;
memset(fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
header->length = sizeof(acpi_fadt_t);
header->revision = 5;
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
memcpy(header->asl_compiler_id, ASLC, 4);
header->asl_compiler_revision = 1;
fadt->firmware_ctrl = (u32)facs;
fadt->dsdt = (u32)dsdt;
fadt->model = 1;
fadt->preferred_pm_profile = PM_MOBILE;
fadt->x_firmware_ctl_l = (u32)facs;
fadt->x_firmware_ctl_h = 0;
fadt->x_dsdt_l = (u32)dsdt;
fadt->x_dsdt_h = 0;
acpi_fill_in_fadt(fadt);
header->checksum = acpi_checksum((void *)fadt, header->length);
}

120
src/mainboard/purism/librem13/gpio.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
#include <soc/gpio.h>
static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_INPUT, /* 0 */
PCH_GPIO_INPUT, /* 1 */
PCH_GPIO_INPUT, /* 2 */
PCH_GPIO_INPUT, /* 3 */
PCH_GPIO_INPUT, /* 4 */
PCH_GPIO_INPUT, /* 5 */
PCH_GPIO_INPUT, /* 6 */
PCH_GPIO_INPUT, /* 7 */
PCH_GPIO_INPUT, /* 8 */
PCH_GPIO_INPUT, /* 9 */
PCH_GPIO_ACPI_SCI, /* 10 */
PCH_GPIO_INPUT, /* 11 */
PCH_GPIO_INPUT, /* 12 */
PCH_GPIO_INPUT, /* 13 */
PCH_GPIO_INPUT, /* 14 */
PCH_GPIO_INPUT, /* 15 */
PCH_GPIO_INPUT, /* 16 */
PCH_GPIO_INPUT, /* 17 */
PCH_GPIO_NATIVE, /* 18 */
PCH_GPIO_NATIVE, /* 19 */
PCH_GPIO_INPUT, /* 20 */
PCH_GPIO_INPUT, /* 21 */
PCH_GPIO_INPUT, /* 22 */
PCH_GPIO_INPUT, /* 23 */
PCH_GPIO_INPUT, /* 24 */
PCH_GPIO_INPUT, /* 25 */
PCH_GPIO_INPUT, /* 26 */
PCH_GPIO_INPUT, /* 27 */
PCH_GPIO_INPUT, /* 28 */
PCH_GPIO_NATIVE, /* 29 */
PCH_GPIO_NATIVE, /* 30 */
PCH_GPIO_NATIVE, /* 31 */
PCH_GPIO_INPUT, /* 32 */
PCH_GPIO_INPUT, /* 33 */
PCH_GPIO_INPUT, /* 34 */
PCH_GPIO_NATIVE, /* 35 */
PCH_GPIO_NATIVE, /* 36 */
PCH_GPIO_NATIVE, /* 37 */
PCH_GPIO_INPUT, /* 38 */
PCH_GPIO_NATIVE, /* 39 */
PCH_GPIO_NATIVE, /* 40 */
PCH_GPIO_INPUT, /* 41 */
PCH_GPIO_INPUT, /* 42 */
PCH_GPIO_INPUT, /* 43 */
PCH_GPIO_INPUT, /* 44 */
PCH_GPIO_INPUT, /* 45 */
PCH_GPIO_INPUT, /* 46 */
PCH_GPIO_INPUT, /* 47 */
PCH_GPIO_INPUT, /* 48 */
PCH_GPIO_INPUT, /* 49 */
PCH_GPIO_INPUT, /* 50 */
PCH_GPIO_INPUT, /* 51 */
PCH_GPIO_INPUT, /* 52 */
PCH_GPIO_INPUT, /* 53 */
PCH_GPIO_INPUT, /* 54 */
PCH_GPIO_INPUT, /* 55 */
PCH_GPIO_INPUT, /* 56 */
PCH_GPIO_INPUT, /* 57 */
PCH_GPIO_INPUT, /* 58 */
PCH_GPIO_INPUT, /* 59 */
PCH_GPIO_INPUT, /* 60 */
PCH_GPIO_NATIVE, /* 61 */
PCH_GPIO_NATIVE, /* 62 */
PCH_GPIO_NATIVE, /* 63 */
PCH_GPIO_INPUT, /* 64 */
PCH_GPIO_INPUT, /* 65 */
PCH_GPIO_INPUT, /* 66 */
PCH_GPIO_INPUT, /* 67 */
PCH_GPIO_INPUT, /* 68 */
PCH_GPIO_INPUT, /* 69 */
PCH_GPIO_INPUT, /* 70 */
PCH_GPIO_NATIVE, /* 71 */
PCH_GPIO_NATIVE, /* 72 */
PCH_GPIO_INPUT, /* 73 */
PCH_GPIO_NATIVE, /* 74 */
PCH_GPIO_NATIVE, /* 75 */
PCH_GPIO_NATIVE, /* 76 */
PCH_GPIO_INPUT, /* 77 */
PCH_GPIO_INPUT, /* 78 */
PCH_GPIO_INPUT, /* 79 */
PCH_GPIO_INPUT, /* 80 */
PCH_GPIO_NATIVE, /* 81 */
PCH_GPIO_NATIVE, /* 82 */
PCH_GPIO_INPUT, /* 83 */
PCH_GPIO_INPUT, /* 84 */
PCH_GPIO_INPUT, /* 85 */
PCH_GPIO_INPUT, /* 86 */
PCH_GPIO_INPUT, /* 87 */
PCH_GPIO_INPUT, /* 88 */
PCH_GPIO_INPUT, /* 89 */
PCH_GPIO_INPUT, /* 90 */
PCH_GPIO_INPUT, /* 91 */
PCH_GPIO_INPUT, /* 92 */
PCH_GPIO_INPUT, /* 93 */
PCH_GPIO_INPUT, /* 94 */
PCH_GPIO_END
};
#endif

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src/mainboard/purism/librem13/hda_verb.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
/* coreboot specific header */
0x19910269, /* Codec Vendor / Device ID: Realtek ALC269 */
0x19910269, /* Subsystem ID */
0x0000000c, /* Number of jacks (NID entries) */
0x0017ff00, /* Function Reset */
0x0017ff00, /* Double Function Reset */
0x0017ff00,
0x0017ff00,
/* Bits 31:28 - Codec Address */
/* Bits 27:20 - NID */
/* Bits 19:8 - Verb ID */
/* Bits 7:0 - Payload */
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x19910269 */
0x00172069,
0x00172102,
0x00172291,
0x00172319,
/* Pin Widget Verb Table */
/* Pin Complex (NID 0x12) */
0x01271c00,
0x01271d00,
0x01271e00,
0x01271f40,
/* Pin Complex (NID 0x14) */
0x01471c10,
0x01471d01,
0x01471e17,
0x01471f90,
/* Pin Complex (NID 0x17) */
0x01771cf0,
0x01771d11,
0x01771e11,
0x01771f41,
/* Pin Complex (NID 0x18) */
0x01871c20,
0x01871d10,
0x01871ea1,
0x01871f04,
/* Pin Complex (NID 0x19) */
0x01971c30,
0x01971d01,
0x01971ea7,
0x01971f90,
/* Pin Complex (NID 0x1A) */
0x01a71cf0,
0x01a71d11,
0x01a71e11,
0x01a71f41,
/* Pin Complex (NID 0x1B) */
0x01b71cf0,
0x01b71d11,
0x01b71e11,
0x01b71f41,
/* Pin Complex (NID 0x1D) */
0x01d71c05,
0x01d71d9d,
0x01d71e56,
0x01d71f40,
/* Pin Complex (NID 0x1E) */
0x01e71cf0,
0x01e71d11,
0x01e71e11,
0x01e71f41,
/* Pin Complex (NID 0x21) */
0x02171c1f,
0x02171d10,
0x02171e21,
0x02171f04,
};
const u32 pc_beep_verbs[] = {};
AZALIA_ARRAY_SIZES;

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src/mainboard/purism/librem13/mainboard.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/device.h>
#include <drivers/intel/gma/int15.h>
static void mainboard_enable(struct device *dev)
{
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP,
GMA_INT15_PANEL_FIT_CENTERING,
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

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src/mainboard/purism/librem13/pei_data.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
pei_data->ec_present = 1;
/* One DIMM slot */
pei_data->dimm_channel1_disabled = 3;
pei_data->spd_addresses[0] = 0xa0;
/* P1: Left Side Port (USB2 only) */
pei_data_usb2_port(pei_data, 0, 0x0080, 1, USB_OC_PIN_SKIP,
USB_PORT_BACK_PANEL);
/* P2: Right Side Port (USB2) */
pei_data_usb2_port(pei_data, 1, 0x0080, 1, USB_OC_PIN_SKIP,
USB_PORT_BACK_PANEL);
/* P3: Empty */
pei_data_usb2_port(pei_data, 2, 0x0000, 0, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
/* P4: Camera */
pei_data_usb2_port(pei_data, 3, 0x0080, 1, USB_OC_PIN_SKIP,
USB_PORT_BACK_PANEL);
/* P5: Bluetooth */
pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP,
USB_PORT_BACK_PANEL);
/* P6: Empty */
pei_data_usb2_port(pei_data, 5, 0x0080, 0, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
/* P7: Empty */
pei_data_usb2_port(pei_data, 6, 0x0080, 0, USB_OC_PIN_SKIP,
USB_PORT_SKIP);
/* P8: SD Card */
pei_data_usb2_port(pei_data, 7, 0x0080, 1, USB_OC_PIN_SKIP,
USB_PORT_BACK_PANEL);
/* P1: Empty */
pei_data_usb3_port(pei_data, 0, 0, USB_OC_PIN_SKIP, 0);
/* P2: Right Side Port (USB3) */
pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0);
/* P3: Empty */
pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
/* P4: Empty */
pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
}

37
src/mainboard/purism/librem13/romstage.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <string.h>
#include <soc/gpio.h>
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
#include <soc/romstage.h>
#include "gpio.h"
void mainboard_romstage_entry(struct romstage_params *rp)
{
struct pei_data pei_data;
/* Initialize GPIOs */
init_gpios(mainboard_gpio_config);
/* Fill out PEI DATA */
memset(&pei_data, 0, sizeof(pei_data));
mainboard_fill_pei_data(&pei_data);
rp->pei_data = &pei_data;
/* Initialize memory */
romstage_common(rp);
}