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mb/google/brya/var/vell: Disable PCH USB2 phy power gating 

The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for vell board. Please refer Intel doc#723158 for
more information.

BUG=b:293535284
TEST=build and boot vell

Change-Id: I8a4d633fbd362188aedef373e515c7bfe5c4327a
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Shon Wang 2023-07-28 11:27:32 +08:00 committed by Felix Held
parent 91f5da4776
commit 27830d0ec3
1 changed files with 4 additions and 0 deletions
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4
src/mainboard/google/brya/variants/vell/overridetree.cb
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@ -71,6 +71,10 @@ chip soc/intel/alderlake
register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC3)" register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC3)"
register "sagv" = "SaGv_Enabled" register "sagv" = "SaGv_Enabled"
# As per Intel Advisory doc#723158, the change is required to prevent possible
# display flickering issue.
register "usb2_phy_sus_pg_disable" = "1"
# Set EPP to 50%: 50 * 256 / 100 = 0x80 # Set EPP to 50%: 50 * 256 / 100 = 0x80
register "enable_energy_perf_pref" = "true" register "enable_energy_perf_pref" = "true"
register "energy_perf_pref_value" = "0x80" register "energy_perf_pref_value" = "0x80"