Support for the Intel 945 northbridge.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
00a889c8aa
commit
278534d007
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2007-2008 coresystems GmbH
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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config chip.h
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driver northbridge.o
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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struct northbridge_intel_i945_config {
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};
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extern struct chip_operations northbridge_intel_i945_ops;
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "i945.h"
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#include "pcie_config.c"
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static int i945_silicon_revision(void)
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{
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return pci_read_config8(PCI_DEV(0, 0x00, 0), 8);
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}
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static void i945_detect_chipset(void)
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{
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u8 reg8;
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printk_info("\r\n");
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reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4;
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switch (reg8) {
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case 1:
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printk_info("Mobile Intel(R) 945GM/GME Express");
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break;
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case 2:
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printk_info("Mobile Intel(R) 945GMS/GU Express");
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break;
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case 3:
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printk_info("Mobile Intel(R) 945PM Express");
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break;
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case 5:
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printk_info("Intel(R) 945GT Express");
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break;
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case 6:
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printk_info("Mobile Intel(R) 943/940GML Express");
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break;
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default:
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printk_info("Unknown (%02x)", reg8); /* Others reserved. */
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}
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printk_info(" Chipset\r\n");
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printk_debug("(G)MCH capable of up to FSB ");
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reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe3) & 0xe0) >> 5;
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switch (reg8) {
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case 2:
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printk_debug("800 MHz"); /* According to 965 spec */
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break;
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case 3:
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printk_debug("667 MHz");
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break;
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case 4:
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printk_debug("533 MHz");
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break;
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default:
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printk_debug("N/A MHz (%02x)", reg8);
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}
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printk_debug("\r\n");
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printk_debug("(G)MCH capable of ");
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reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07);
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switch (reg8) {
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case 2:
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printk_debug("up to DDR2-667");
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break;
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case 3:
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printk_debug("up to DDR2-533");
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break;
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case 4:
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printk_debug("DDR2-400");
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break;
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default:
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printk_info("unknown max. RAM clock (%02x).", reg8); /* Others reserved. */
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}
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printk_debug("\r\n");
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}
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static void i945_setup_bars(void)
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{
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u8 reg8;
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/* As of now, we don't have all the A0 workarounds implemented */
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if (i945_silicon_revision() == 0)
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printk_info
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("Warning: i945 silicon revision A0 might not work correctly.\r\n");
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/* Setting up Southbridge. In the northbridge code. */
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printk_debug("Setting up static southbridge registers...");
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pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
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pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); /* Enable GPIOs */
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setup_ich7_gpios();
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printk_debug(" done.\r\n");
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printk_debug("Disabling Watchdog reboot...");
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RCBA32(GCS) = (RCBA32(0x3410)) | (1 << 5); /* No reset */
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outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */
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printk_debug(" done.\r\n");
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printk_debug("Setting up static northbridge registers...");
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/* Set up all hardcoded northbridge BARs */
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pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
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pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
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pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */
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pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
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pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1);
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/* Hardware default is 8MB UMA. If someone wants to make this a
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* CMOS or compile time option, send a patch.
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* pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, 0x30);
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*/
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/* Set C0000-FFFFF to access RAM on both reads and writes */
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pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);
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pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33);
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pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33);
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pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33);
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pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33);
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pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33);
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pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
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pci_write_config8(PCI_DEV(0, 0x00, 0), TOLUD, 0x40); /* 1G XXX dynamic! */
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pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
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printk_debug(" done.\r\n");
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/* Wait for MCH BAR to come up */
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printk_debug("Waiting for MCHBAR to come up...");
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if ((pci_read_config8(PCI_DEV(0, 0x0f, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */
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do {
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reg8 = *(volatile u8 *)0xfed40000;
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} while (!(reg8 & 0x80));
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}
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printk_debug("ok\r\n");
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}
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static void i945_setup_egress_port(void)
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{
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u32 reg32;
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u32 timeout;
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printk_debug("Setting up Egress Port RCRB\n");
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/* Egress Port Virtual Channel 0 Configuration */
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/* map only TC0 to VC0 */
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reg32 = EPBAR32(EPVC0RCTL);
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reg32 &= 0xffffff01;
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EPBAR32(EPVC0RCTL) = reg32;
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reg32 = EPBAR32(EPPVCCAP1);
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reg32 &= ~(7 << 0);
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reg32 |= 1;
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EPBAR32(EPPVCCAP1) = reg32;
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/* Egress Port Virtual Channel 1 Configuration */
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reg32 = EPBAR32(0x2c);
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reg32 &= 0xffffff00;
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if ((MCHBAR32(CLKCFG) & 7) == 1)
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reg32 |= 0x0d; /* 533MHz */
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if ((MCHBAR32(CLKCFG) & 7) == 3)
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reg32 |= 0x10; /* 667MHz */
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EPBAR32(0x2c) = reg32;
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EPBAR32(EPVC1MTS) = 0x0a0a0a0a;
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reg32 = EPBAR32(EPVC1RCAP);
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reg32 &= ~(0x7f << 16);
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reg32 |= (0x0a << 16);
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EPBAR32(EPVC1RCAP) = reg32;
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if ((MCHBAR32(CLKCFG) & 7) == 1) { /* 533MHz */
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EPBAR32(EPVC1IST + 0) = 0x009c009c;
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EPBAR32(EPVC1IST + 4) = 0x009c009c;
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}
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if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */
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EPBAR32(EPVC1IST + 0) = 0x00c000c0;
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EPBAR32(EPVC1IST + 4) = 0x00c000c0;
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}
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/* Is internal graphics enabled? */
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if (pci_read_config8(PCI_DEV(0, 0x0, 0), 54) & ((1 << 4) | (1 << 3))) { /* DEVEN */
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MCHBAR32(MMARB1) |= (1 << 17);
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}
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/* Assign Virtual Channel ID 1 to VC1 */
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reg32 = EPBAR32(EPVC1RCTL);
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reg32 &= ~(7 << 24);
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reg32 |= (1 << 24);
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EPBAR32(EPVC1RCTL) = reg32;
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reg32 = EPBAR32(EPVC1RCTL);
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reg32 &= 0xffffff01;
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reg32 |= (1 << 7);
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EPBAR32(EPVC1RCTL) = reg32;
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EPBAR32(PORTARB + 0x00) = 0x01000001;
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EPBAR32(PORTARB + 0x04) = 0x00040000;
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EPBAR32(PORTARB + 0x08) = 0x00001000;
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EPBAR32(PORTARB + 0x0c) = 0x00000040;
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EPBAR32(PORTARB + 0x10) = 0x01000001;
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EPBAR32(PORTARB + 0x14) = 0x00040000;
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EPBAR32(PORTARB + 0x18) = 0x00001000;
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EPBAR32(PORTARB + 0x1c) = 0x00000040;
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EPBAR32(EPVC1RCTL) |= (1 << 16);
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EPBAR32(EPVC1RCTL) |= (1 << 16);
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printk_debug("Loading port arbitration table ...");
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/* Loop until bit 0 becomes 0 */
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timeout = 0x7fffff;
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while ((EPBAR16(EPVC1RSTS) & 1) && --timeout) ;
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if (!timeout)
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printk_debug("timeout!\n");
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else
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printk_debug("ok\n");
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/* Now enable VC1 */
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EPBAR32(EPVC1RCTL) |= (1 << 31);
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printk_debug("Wait for VC1 negotiation ...");
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/* Wait for VC1 negotiation pending */
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timeout = 0x7fff;
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while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout) ;
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if (!timeout)
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printk_debug("timeout!\n");
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else
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printk_debug("ok\n");
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}
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static void ich7_setup_dmi_rcrb(void)
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{
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u16 reg16;
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reg16 = RCBA16(LCTL);
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reg16 &= ~(3 << 0);
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reg16 |= 1;
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RCBA16(LCTL) = reg16;
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RCBA32(V0CTL) = 0x80000001;
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RCBA32(V1CAP) = 0x03128010;
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RCBA32(ESD) = 0x00000810;
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RCBA32(RP1D) = 0x01000003;
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RCBA32(RP2D) = 0x02000002;
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RCBA32(RP3D) = 0x03000002;
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RCBA32(RP4D) = 0x04000002;
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RCBA32(HDD) = 0x0f000003;
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RCBA32(RP5D) = 0x05000002;
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RCBA32(RPFN) = 0x00543210;
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pci_write_config16(PCI_DEV(0, 0x1c, 0), 0x42, 0x0141);
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pci_write_config16(PCI_DEV(0, 0x1c, 4), 0x42, 0x0141);
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pci_write_config16(PCI_DEV(0, 0x1c, 5), 0x42, 0x0141);
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pci_write_config32(PCI_DEV(0, 0x1c, 4), 0x54, 0x00480ce0);
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pci_write_config32(PCI_DEV(0, 0x1c, 5), 0x54, 0x00500ce0);
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}
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static void i945_setup_dmi_rcrb(void)
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{
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u32 reg32;
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u32 timeout;
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printk_debug("Setting up DMI RCRB\n");
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/* Virtual Channel 0 Configuration */
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reg32 = DMIBAR32(DMIVC0RCTL0);
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reg32 &= 0xffffff01;
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DMIBAR32(DMIVC0RCTL0) = reg32;
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reg32 = DMIBAR32(DMIPVCCAP1);
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reg32 &= ~(7 << 0);
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reg32 |= 1;
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DMIBAR32(DMIPVCCAP1) = reg32;
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reg32 = DMIBAR32(DMIVC1RCTL);
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reg32 &= ~(7 << 24);
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reg32 |= (1 << 24); /* NOTE: This ID must match ICH7 side */
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DMIBAR32(DMIVC1RCTL) = reg32;
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reg32 = DMIBAR32(DMIVC1RCTL);
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reg32 &= 0xffffff01;
|
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reg32 |= (1 << 7);
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DMIBAR32(DMIVC1RCTL) = reg32;
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|
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/* Now enable VC1 */
|
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DMIBAR32(DMIVC1RCTL) |= (1 << 31);
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|
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printk_debug("Wait for VC1 negotiation ...");
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/* Wait for VC1 negotiation pending */
|
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timeout = 0x7ffff;
|
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while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout) ;
|
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if (!timeout)
|
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printk_debug("timeout!\n");
|
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else
|
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printk_debug("done..\n");
|
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#if 1
|
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/* Enable Active State Power Management (ASPM) L0 state */
|
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|
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reg32 = DMIBAR32(DMILCAP);
|
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reg32 &= ~(7 << 12);
|
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reg32 |= (2 << 12);
|
||||
|
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reg32 &= ~(7 << 15);
|
||||
|
||||
reg32 |= (2 << 15);
|
||||
DMIBAR32(DMILCAP) = reg32;
|
||||
|
||||
reg32 = DMIBAR32(DMICC);
|
||||
reg32 &= 0x00ffffff;
|
||||
reg32 &= ~(3 << 0);
|
||||
reg32 |= (1 << 0);
|
||||
DMIBAR32(DMICC) = reg32;
|
||||
|
||||
if (0) {
|
||||
DMIBAR32(DMILCTL) |= (3 << 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Last but not least, some additional steps */
|
||||
reg32 = MCHBAR32(FSBSNPCTL);
|
||||
reg32 &= ~(0xff << 2);
|
||||
reg32 |= (0xaa << 2);
|
||||
MCHBAR32(FSBSNPCTL) = reg32;
|
||||
|
||||
DMIBAR32(0x2c) = 0x86000040;
|
||||
|
||||
reg32 = DMIBAR32(0x204);
|
||||
reg32 &= ~0x3ff;
|
||||
#if 1
|
||||
reg32 |= 0x13f; /* for x4 DMI only */
|
||||
#else
|
||||
reg32 |= 0x1e4; /* for x2 DMI only */
|
||||
#endif
|
||||
DMIBAR32(0x204) = reg32;
|
||||
|
||||
if (pci_read_config8(PCI_DEV(0, 0x0, 0), 54) & ((1 << 4) | (1 << 3))) { /* DEVEN */
|
||||
DMIBAR32(0x200) |= (1 << 21);
|
||||
} else {
|
||||
DMIBAR32(0x200) &= ~(1 << 21);
|
||||
}
|
||||
|
||||
reg32 = DMIBAR32(0x204);
|
||||
reg32 &= ~((1 << 11) | (1 << 10));
|
||||
DMIBAR32(0x204) = reg32;
|
||||
|
||||
reg32 = DMIBAR32(0x204);
|
||||
reg32 &= ~(0xff << 12);
|
||||
reg32 |= (0x0d << 12);
|
||||
DMIBAR32(0x204) = reg32;
|
||||
|
||||
DMIBAR32(DMICTL1) |= (3 << 24);
|
||||
|
||||
reg32 = DMIBAR32(0x200);
|
||||
reg32 &= ~(0x3 << 26);
|
||||
reg32 |= (0x02 << 26);
|
||||
DMIBAR32(0x200) = reg32;
|
||||
|
||||
DMIBAR32(DMIDRCCFG) &= ~(1 << 31);
|
||||
DMIBAR32(DMICTL2) |= (1 << 31);
|
||||
|
||||
if (i945_silicon_revision() >= 3) {
|
||||
reg32 = DMIBAR32(0xec0);
|
||||
reg32 &= 0x0fffffff;
|
||||
reg32 |= (2 << 28);
|
||||
DMIBAR32(0xec0) = reg32;
|
||||
|
||||
reg32 = DMIBAR32(0xed4);
|
||||
reg32 &= 0x0fffffff;
|
||||
reg32 |= (2 << 28);
|
||||
DMIBAR32(0xed4) = reg32;
|
||||
|
||||
reg32 = DMIBAR32(0xee8);
|
||||
reg32 &= 0x0fffffff;
|
||||
reg32 |= (2 << 28);
|
||||
DMIBAR32(0xee8) = reg32;
|
||||
|
||||
reg32 = DMIBAR32(0xefc);
|
||||
reg32 &= 0x0fffffff;
|
||||
reg32 |= (2 << 28);
|
||||
DMIBAR32(0xefc) = reg32;
|
||||
}
|
||||
|
||||
/* wait for bit toggle to 0 */
|
||||
printk_debug("Waiting for DMI hardware...");
|
||||
timeout = 0x7fffff;
|
||||
while ((DMIBAR8(0x32) & (1 << 1)) && --timeout) ;
|
||||
if (!timeout)
|
||||
printk_debug("timeout!\n");
|
||||
else
|
||||
printk_debug("ok\n");
|
||||
|
||||
DMIBAR32(0x1c4) = 0xffffffff;
|
||||
DMIBAR32(0x1d0) = 0xffffffff;
|
||||
DMIBAR32(0x228) = 0xffffffff;
|
||||
|
||||
DMIBAR32(0x308) = DMIBAR32(0x308);
|
||||
DMIBAR32(0x314) = DMIBAR32(0x314);
|
||||
DMIBAR32(0x324) = DMIBAR32(0x324);
|
||||
DMIBAR32(0x328) = DMIBAR32(0x328);
|
||||
DMIBAR32(0x338) = DMIBAR32(0x334);
|
||||
DMIBAR32(0x338) = DMIBAR32(0x338);
|
||||
|
||||
if (i945_silicon_revision() == 1 && ((MCHBAR8(0xe08) & (1 << 5)) == 1)) {
|
||||
if ((MCHBAR32(0x214) & 0xf) != 0x3) {
|
||||
printk_info
|
||||
("DMI link requires A1 stepping workaround. Rebooting.\n");
|
||||
reg32 = MCHBAR32(MMARB1);
|
||||
reg32 &= 0xfffffff8;
|
||||
reg32 |= 3;
|
||||
outb(0x06, 0xcf9);
|
||||
for (;;) ; /* wait for reset */
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void i945_setup_pci_express_x16(void)
|
||||
{
|
||||
u32 timeout;
|
||||
u32 reg32;
|
||||
u16 reg16;
|
||||
u8 reg8;
|
||||
|
||||
/* For now we just disable the x16 link */
|
||||
printk_debug("Disabling PCI Express x16 Link\n");
|
||||
|
||||
MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0);
|
||||
|
||||
reg8 = pcie_read_config8(PCI_DEV(0, 0x01, 0), BCTRL1);
|
||||
reg8 |= (1 << 6);
|
||||
pcie_write_config8(PCI_DEV(0, 0x01, 0), BCTRL1, reg8);
|
||||
|
||||
reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x224);
|
||||
reg32 |= (1 << 8);
|
||||
pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32);
|
||||
|
||||
reg8 = pcie_read_config8(PCI_DEV(0, 0x01, 0), BCTRL1);
|
||||
reg8 &= ~(1 << 6);
|
||||
pcie_write_config8(PCI_DEV(0, 0x01, 0), BCTRL1, reg8);
|
||||
|
||||
printk_debug("Wait for link to enter detect state... ");
|
||||
timeout = 0x7fffff;
|
||||
for (reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214);
|
||||
(reg32 & 0x000f0000) && --timeout;) ;
|
||||
if (!timeout)
|
||||
printk_debug("timeout!\n");
|
||||
else
|
||||
printk_debug("ok\n");
|
||||
|
||||
/* Finally: Disable the PCI config header */
|
||||
reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN);
|
||||
reg16 &= ~DEVEN_D1F0;
|
||||
pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16);
|
||||
}
|
||||
|
||||
static void i945_setup_root_complex_topology(void)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
printk_debug("Setting up Root Complex Topology\n");
|
||||
/* Egress Port Root Topology */
|
||||
reg32 = EPBAR32(EPESD);
|
||||
reg32 &= 0xff00ffff;
|
||||
reg32 |= (1 << 16);
|
||||
EPBAR32(EPESD) = reg32;
|
||||
|
||||
EPBAR32(EPLE1D) |= (1 << 0);
|
||||
|
||||
EPBAR32(EPLE1A) = DEFAULT_PCIEXBAR + 0x4000;
|
||||
|
||||
EPBAR32(EPLE2D) |= (1 << 0);
|
||||
|
||||
/* DMI Port Root Topology */
|
||||
reg32 = DMIBAR32(DMILE1D);
|
||||
reg32 &= 0x00ffffff;
|
||||
DMIBAR32(DMILE1D) = reg32;
|
||||
|
||||
reg32 = DMIBAR32(DMILE1D);
|
||||
reg32 &= 0xff00ffff;
|
||||
reg32 |= (2 << 16);
|
||||
DMIBAR32(DMILE1D) = reg32;
|
||||
|
||||
DMIBAR32(DMILE1D) |= (1 << 0);
|
||||
|
||||
DMIBAR32(DMILE1A) = DEFAULT_PCIEXBAR + 0x8000;
|
||||
|
||||
DMIBAR32(DMILE2D) |= (1 << 0);
|
||||
|
||||
DMIBAR32(DMILE2A) = DEFAULT_PCIEXBAR + 0x5000;
|
||||
|
||||
/* PCI Express x16 Port Root Topology */
|
||||
if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) {
|
||||
pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x158,
|
||||
DEFAULT_PCIEXBAR + 0x5000);
|
||||
|
||||
reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x150);
|
||||
reg32 |= (1 << 0);
|
||||
pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x150, reg32);
|
||||
}
|
||||
}
|
||||
|
||||
static void ich7_setup_root_complex_topology(void)
|
||||
{
|
||||
RCBA32(0x104) = 0x00000802;
|
||||
RCBA32(0x110) = 0x00000001;
|
||||
RCBA32(0x114) = 0x00000000;
|
||||
RCBA32(0x118) = 0x00000000;
|
||||
}
|
||||
|
||||
static void ich7_setup_pci_express(void)
|
||||
{
|
||||
RCBA32(CG) |= (1 << 0);
|
||||
|
||||
pci_write_config32(PCI_DEV(0, 0x1c, 0), 0x54, 0x00000060);
|
||||
|
||||
pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000);
|
||||
}
|
||||
|
||||
static void i945_early_initialization(void)
|
||||
{
|
||||
/* Print some chipset specific information */
|
||||
i945_detect_chipset();
|
||||
|
||||
/* Setup all BARs required for early PCIe and raminit */
|
||||
i945_setup_bars();
|
||||
|
||||
/* Change port80 to LPC */
|
||||
RCBA32(GCS) &= (~0x04);
|
||||
}
|
||||
|
||||
static void i945_late_initialization(void)
|
||||
{
|
||||
i945_setup_egress_port();
|
||||
|
||||
ich7_setup_root_complex_topology();
|
||||
|
||||
ich7_setup_pci_express();
|
||||
|
||||
ich7_setup_dmi_rcrb();
|
||||
|
||||
i945_setup_dmi_rcrb();
|
||||
|
||||
i945_setup_pci_express_x16();
|
||||
|
||||
i945_setup_root_complex_topology();
|
||||
}
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2008 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
int fixup_i945_errata(void)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
/* Mobile Intel 945 Express only */
|
||||
reg32 = MCHBAR32(FSBPMC3);
|
||||
reg32 &= ~((1 << 13) | (1 << 29));
|
||||
MCHBAR32(FSBPMC3) = reg32;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,330 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2008 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef __NORTHBRIDGE_INTEL_I945_I945_H__
|
||||
#define __NORTHBRIDGE_INTEL_I945_I945_H__ 1
|
||||
|
||||
#include "ich7.h"
|
||||
|
||||
/* Device 0:0.0 PCI configuration space (Host Bridge) */
|
||||
|
||||
#define EPBAR 0x40
|
||||
#define MCHBAR 0x44
|
||||
#define PCIEXBAR 0x48
|
||||
#define DMIBAR 0x4c
|
||||
#define X60BAR 0x60
|
||||
|
||||
/* Northbridge BARs */
|
||||
#define DEFAULT_PCIEXBAR 0xf0000000
|
||||
#define DEFAULT_X60BAR 0xfed13000
|
||||
#define DEFAULT_MCHBAR 0xfed14000
|
||||
#define DEFAULT_DMIBAR 0xfed18000
|
||||
#define DEFAULT_EPBAR 0xfed19000
|
||||
|
||||
#define GGC 0x52
|
||||
|
||||
#define DEVEN 0x54
|
||||
#define DEVEN_D0F0 (1 << 0)
|
||||
#define DEVEN_D1F0 (1 << 1)
|
||||
#define DEVEN_D2F0 (1 << 3)
|
||||
#define DEVEN_D2F1 (1 << 4)
|
||||
#ifndef BOARD_DEVEN
|
||||
#define BOARD_DEVEN ( DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1 )
|
||||
#endif
|
||||
|
||||
#define PAM0 0x90
|
||||
#define PAM1 0x91
|
||||
#define PAM2 0x92
|
||||
#define PAM3 0x93
|
||||
#define PAM4 0x94
|
||||
#define PAM5 0x95
|
||||
#define PAM6 0x96
|
||||
|
||||
#define LAC 0x97 /* Legacy Access Control */
|
||||
#define TOLUD 0x9c /* Top of Low Used Memory */
|
||||
#define SMRAM 0x9d
|
||||
#define ESMRAM 0x9e
|
||||
|
||||
#define TOM 0xa0
|
||||
|
||||
#define SKPAD 0xdc /* Scratchpad */
|
||||
|
||||
/* Device 0:1.0 PCI configuration space (PCI Express) */
|
||||
|
||||
#define BCTRL1 0x3e /* 8bit */
|
||||
|
||||
|
||||
/* Device 0:2.0 PCI configuration space (Graphics Device) */
|
||||
|
||||
#define GCFC 0xf0 /* Graphics Clock Frequency and Gating Control */
|
||||
|
||||
|
||||
/*
|
||||
* MCHBAR
|
||||
*/
|
||||
|
||||
#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))
|
||||
#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))
|
||||
#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))
|
||||
|
||||
/* Chipset Control Registers */
|
||||
#define FSBPMC3 0x40 /* 32bit */
|
||||
#define FSBPMC4 0x44 /* 32bit */
|
||||
#define FSBSNPCTL 0x48 /* 32bit */
|
||||
#define SLPCTL 0x90 /* 32bit */
|
||||
|
||||
#define C0DRB0 0x100 /* 8bit */
|
||||
#define C0DRB1 0x101 /* 8bit */
|
||||
#define C0DRB2 0x102 /* 8bit */
|
||||
#define C0DRB3 0x103 /* 8bit */
|
||||
#define C0DRA0 0x108 /* 8bit */
|
||||
#define C0DRA2 0x109 /* 8bit */
|
||||
#define C0DCLKDIS 0x10c /* 8bit */
|
||||
#define C0BNKARC 0x10e /* 16bit */
|
||||
#define C0DRT0 0x110 /* 32bit */
|
||||
#define C0DRT1 0x114 /* 32bit */
|
||||
#define C0DRT2 0x118 /* 32bit */
|
||||
#define C0DRT3 0x11c /* 32bit */
|
||||
#define C0DRC0 0x120 /* 32bit */
|
||||
#define C0DRC1 0x124 /* 32bit */
|
||||
#define C0DRC2 0x128 /* 32bit */
|
||||
#define C0AIT 0x130 /* 64bit */
|
||||
#define C0DCCFT 0x138 /* 64bit */
|
||||
#define C0GTEW 0x140 /* 32bit */
|
||||
#define C0GTC 0x144 /* 32bit */
|
||||
#define C0DTPEW 0x148 /* 64bit */
|
||||
#define C0DTAEW 0x150 /* 64bit */
|
||||
#define C0DTC 0x158 /* 32bit */
|
||||
#define C0DMC 0x164 /* 32bit */
|
||||
#define C0ODT 0x168 /* 64bit */
|
||||
|
||||
#define C1DRB0 0x180 /* 8bit */
|
||||
#define C1DRB1 0x181 /* 8bit */
|
||||
#define C1DRB2 0x182 /* 8bit */
|
||||
#define C1DRB3 0x183 /* 8bit */
|
||||
#define C1DRA0 0x188 /* 8bit */
|
||||
#define C1DCLKDIS 0x18c /* 8bit */
|
||||
#define C1BNKARC 0x18e /* 16bit */
|
||||
#define C1DRT0 0x190 /* 32bit */
|
||||
#define C1DRT1 0x194 /* 32bit */
|
||||
#define C1DRT2 0x198 /* 32bit */
|
||||
#define C1DRT3 0x19c /* 32bit */
|
||||
#define C1DRC0 0x1a0 /* 32bit */
|
||||
#define C1DRC1 0x1a4 /* 32bit */
|
||||
#define C1DRC2 0x1a8 /* 32bit */
|
||||
#define C1AIT 0x1b0 /* 64bit */
|
||||
#define C1DCCFT 0x1b8 /* 64bit */
|
||||
#define C1GTEW 0x1c0 /* 32bit */
|
||||
#define C1GTC 0x1c4 /* 32bit */
|
||||
#define C1DTPEW 0x1c8 /* 64bit */
|
||||
#define C1DTAEW 0x1d0 /* 64bit */
|
||||
#define C1DTC 0x1d8 /* 32bit */
|
||||
#define C1DMC 0x1e4 /* 32bit */
|
||||
#define C1ODT 0x1e8 /* 64bit */
|
||||
|
||||
#define DCC 0x200 /* 32bit */
|
||||
#define CCCFT 0x208 /* 64bit */
|
||||
#define WCC 0x218 /* 32bit */
|
||||
#define MMARB0 0x220 /* 32bit */
|
||||
#define MMARB1 0x224 /* 32bit */
|
||||
#define SBTEST 0x230 /* 32bit */
|
||||
#define SBOCC 0x238 /* 32bit */
|
||||
#define ODTC 0x284 /* 32bit */
|
||||
#define SMVREFC 0x2a0 /* 32bit */
|
||||
#define DRTST 0x2a8 /* 32bit */
|
||||
#define REPC 0x2e0 /* 32bit */
|
||||
#define DQSMT 0x2f4 /* 16bit */
|
||||
#define RCVENMT 0x2f8 /* 32bit */
|
||||
|
||||
#define C0R0B00DQST 0x300 /* 64bit */
|
||||
|
||||
#define C0WL0REOST 0x340 /* 8bit */
|
||||
#define C0WL1REOST 0x341 /* 8bit */
|
||||
#define C0WL2REOST 0x342 /* 8bit */
|
||||
#define C0WL3REOST 0x343 /* 8bit */
|
||||
#define WDLLBYPMODE 0x360 /* 16bit */
|
||||
#define C0WDLLCMC 0x36c /* 32bit */
|
||||
#define C0HCTC 0x37c /* 8bit */
|
||||
|
||||
#define C1R0B00DQST 0x380 /* 64bit */
|
||||
|
||||
#define C1WL0REOST 0x3c0 /* 8bit */
|
||||
#define C1WL1REOST 0x3c1 /* 8bit */
|
||||
#define C1WL2REOST 0x3c2 /* 8bit */
|
||||
#define C1WL3REOST 0x3c3 /* 8bit */
|
||||
#define C1WDLLCMC 0x3ec /* 32bit */
|
||||
#define C1HCTC 0x3fc /* 8bit */
|
||||
|
||||
#define GBRCOMPCTL 0x400 /* 32bit */
|
||||
|
||||
#define SMSRCTL 0x408 /* XXX who knows */
|
||||
#define C0DRAMW 0x40c /* 16bit */
|
||||
#define G1SC 0x410 /* 8bit */
|
||||
#define G2SC 0x418 /* 8bit */
|
||||
#define G3SC 0x420 /* 8bit */
|
||||
#define G4SC 0x428 /* 8bit */
|
||||
#define G5SC 0x430 /* 8bit */
|
||||
#define G6SC 0x438 /* 8bit */
|
||||
|
||||
#define C1DRAMW 0x48c /* 16bit */
|
||||
#define G7SC 0x490 /* 8bit */
|
||||
#define G8SC 0x498 /* 8bit */
|
||||
|
||||
#define G1SRPUT 0x500 /* 256bit */
|
||||
#define G1SRPDT 0x520 /* 256bit */
|
||||
#define G2SRPUT 0x540 /* 256bit */
|
||||
#define G2SRPDT 0x560 /* 256bit */
|
||||
#define G3SRPUT 0x580 /* 256bit */
|
||||
#define G3SRPDT 0x5a0 /* 256bit */
|
||||
#define G4SRPUT 0x5c0 /* 256bit */
|
||||
#define G4SRPDT 0x5e0 /* 256bit */
|
||||
#define G5SRPUT 0x600 /* 256bit */
|
||||
#define G5SRPDT 0x620 /* 256bit */
|
||||
#define G6SRPUT 0x640 /* 256bit */
|
||||
#define G6SRPDT 0x660 /* 256bit */
|
||||
#define G7SRPUT 0x680 /* 256bit */
|
||||
#define G7SRPDT 0x6a0 /* 256bit */
|
||||
#define G8SRPUT 0x6c0 /* 256bit */
|
||||
#define G8SRPDT 0x6e0 /* 256bit */
|
||||
|
||||
/* Clock Controls */
|
||||
#define CLKCFG 0xc00 /* 32bit */
|
||||
#define UPMC1 0xc14 /* 16bit */
|
||||
#define CPCTL 0xc16 /* 16bit */
|
||||
#define SSKPD 0xc1c /* 16bit (scratchpad) */
|
||||
#define UPMC2 0xc20 /* 16bit */
|
||||
#define UPMC4 0xc30 /* 32bit */
|
||||
#define PLLMON 0xc34 /* 32bit */
|
||||
#define HGIPMC2 0xc38 /* 32bit */
|
||||
|
||||
/* Thermal Management Controls */
|
||||
#define TSC1 0xc88 /* 8bit */
|
||||
#define TSS1 0xc8a /* 8bit */
|
||||
#define TR1 0xc8b /* 8bit */
|
||||
#define TSTTP1 0xc8c /* 32bit */
|
||||
#define TCO1 0xc92 /* 8bit */
|
||||
#define THERM1_1 0xc94 /* 8bit */
|
||||
#define TCOF1 0xc96 /* 8bit */
|
||||
#define TIS1 0xc9a /* 16bit */
|
||||
#define TSTTP1_2 0xc9c /* 32bit */
|
||||
#define IUB 0xcd0 /* 32bit */
|
||||
#define TSC0_1 0xcd8 /* 8bit */
|
||||
#define TSS0 0xcda /* 8bit */
|
||||
#define TR0 0xcdb /* 8bit */
|
||||
#define TSTTP0_1 0xcdc /* 32bit */
|
||||
#define TCO0 0xce2 /* 8bit */
|
||||
#define THERM0_1 0xce4 /* 8bit */
|
||||
#define TCOF0 0xce6 /* 8bit */
|
||||
#define TIS0 0xcea /* 16bit */
|
||||
#define TSTTP0_2 0xcec /* 32bit */
|
||||
#define TERRCMD 0xcf0 /* 8bit */
|
||||
#define TSMICMD 0xcf1 /* 8bit */
|
||||
#define TSCICMD 0xcf2 /* 8bit */
|
||||
#define TINTRCMD 0xcf3 /* 8bit */
|
||||
#define EXTTSCS 0xcff /* 8bit */
|
||||
#define DFT_STRAP1 0xe08 /* 32bit */
|
||||
|
||||
/* ACPI Power Management Controls */
|
||||
|
||||
#define MIPMC3 0xbd8 /* 32bit */
|
||||
|
||||
#define C2C3TT 0xf00 /* 32bit */
|
||||
#define C3C4TT 0xf04 /* 32bit */
|
||||
|
||||
#define MIPMC4 0xf08 /* 16bit */
|
||||
#define MIPMC5 0xf0a /* 16bit */
|
||||
#define MIPMC6 0xf0c /* 16bit */
|
||||
#define MIPMC7 0xf0e /* 16bit */
|
||||
#define PMCFG 0xf10 /* 32bit */
|
||||
#define SLFRCS 0xf14 /* 32bit */
|
||||
#define GIPMC1 0xfb0 /* 32bit */
|
||||
#define FSBPMC1 0xfb8 /* 32bit */
|
||||
#define UPMC3 0xfc0 /* 32bit */
|
||||
#define ECO 0xffc /* 32bit */
|
||||
|
||||
/*
|
||||
* EPBAR - Egress Port Root Complex Register Block
|
||||
*/
|
||||
|
||||
#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
|
||||
#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
|
||||
#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
|
||||
|
||||
#define EPPVCCAP1 0x004 /* 32bit */
|
||||
#define EPPVCCAP2 0x008 /* 32bit */
|
||||
|
||||
#define EPVC0RCAP 0x010 /* 32bit */
|
||||
#define EPVC0RCTL 0x014 /* 32bit */
|
||||
#define EPVC0RSTS 0x01a /* 16bit */
|
||||
|
||||
#define EPVC1RCAP 0x01c /* 32bit */
|
||||
#define EPVC1RCTL 0x020 /* 32bit */
|
||||
#define EPVC1RSTS 0x026 /* 16bit */
|
||||
|
||||
#define EPVC1MTS 0x028 /* 32bit */
|
||||
#define EPVC1IST 0x038 /* 64bit */
|
||||
|
||||
#define EPESD 0x044 /* 32bit */
|
||||
|
||||
#define EPLE1D 0x050 /* 32bit */
|
||||
#define EPLE1A 0x058 /* 64bit */
|
||||
#define EPLE2D 0x060 /* 32bit */
|
||||
#define EPLE2A 0x068 /* 64bit */
|
||||
|
||||
#define PORTARB 0x100 /* 256bit */
|
||||
|
||||
/*
|
||||
* DMIBAR
|
||||
*/
|
||||
|
||||
#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
|
||||
#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
|
||||
#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
|
||||
|
||||
#define DMIVCECH 0x000 /* 32bit */
|
||||
#define DMIPVCCAP1 0x004 /* 32bit */
|
||||
#define DMIPVCCAP2 0x008 /* 32bit */
|
||||
|
||||
#define DMIPVCCCTL 0x00c /* 16bit */
|
||||
|
||||
#define DMIVC0RCAP 0x010 /* 32bit */
|
||||
#define DMIVC0RCTL0 0x014 /* 32bit */
|
||||
#define DMIVC0RSTS 0x01a /* 16bit */
|
||||
|
||||
#define DMIVC1RCAP 0x01c /* 32bit */
|
||||
#define DMIVC1RCTL 0x020 /* 32bit */
|
||||
#define DMIVC1RSTS 0x026 /* 16bit */
|
||||
|
||||
#define DMILE1D 0x050 /* 32bit */
|
||||
#define DMILE1A 0x058 /* 64bit */
|
||||
#define DMILE2D 0x060 /* 32bit */
|
||||
#define DMILE2A 0x068 /* 64bit */
|
||||
|
||||
#define DMILCAP 0x084 /* 32bit */
|
||||
#define DMILCTL 0x088 /* 16bit */
|
||||
#define DMILSTS 0x08a /* 16bit */
|
||||
|
||||
#define DMICTL1 0x0f0 /* 32bit */
|
||||
#define DMICTL2 0x0fc /* 32bit */
|
||||
|
||||
#define DMICC 0x208 /* 32bit */
|
||||
|
||||
#define DMIDRCCFG 0xeb4 /* 32bit */
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,142 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2008 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef __NORTHBRIDGE_INTEL_I945_ICH7_H__
|
||||
#define __NORTHBRIDGE_INTEL_I945_ICH7_H__ 1
|
||||
|
||||
/* Southbridge IO BARs */
|
||||
/* TODO Make sure these don't get changed by stage2 */
|
||||
#define GPIOBASE 0x48
|
||||
#define DEFAULT_GPIOBASE 0x480
|
||||
|
||||
#define PMBASE 0x40
|
||||
#define DEFAULT_PMBASE 0x500
|
||||
|
||||
/* Root Complex Register Block */
|
||||
#define RCBA 0xf0
|
||||
#define DEFAULT_RCBA 0xfed1c000
|
||||
|
||||
#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
|
||||
#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
|
||||
#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
|
||||
|
||||
#define VCH 0x0000 /* 32bit */
|
||||
#define VCAP1 0x0004 /* 32bit */
|
||||
#define VCAP2 0x0008 /* 32bit */
|
||||
#define PVC 0x000c /* 16bit */
|
||||
#define PVS 0x000e /* 16bit */
|
||||
|
||||
#define V0CAP 0x0010 /* 32bit */
|
||||
#define V0CTL 0x0014 /* 32bit */
|
||||
#define V0STS 0x001a /* 16bit */
|
||||
|
||||
#define V1CAP 0x001c /* 32bit */
|
||||
#define V1CTL 0x0020 /* 32bit */
|
||||
#define V1STS 0x0026 /* 16bit */
|
||||
|
||||
#define RCTCL 0x0100 /* 32bit */
|
||||
#define ESD 0x0104 /* 32bit */
|
||||
#define ULD 0x0110 /* 32bit */
|
||||
#define ULBA 0x0118 /* 64bit */
|
||||
|
||||
#define RP1D 0x0120 /* 32bit */
|
||||
#define RP1BA 0x0128 /* 64bit */
|
||||
#define RP2D 0x0130 /* 32bit */
|
||||
#define RP2BA 0x0138 /* 64bit */
|
||||
#define RP3D 0x0140 /* 32bit */
|
||||
#define RP3BA 0x0138 /* 64bit */
|
||||
#define RP4D 0x0150 /* 32bit */
|
||||
#define RP4BA 0x0158 /* 64bit */
|
||||
#define HDD 0x0160 /* 32bit */
|
||||
#define HDBA 0x0168 /* 64bit */
|
||||
#define RP5D 0x0170 /* 32bit */
|
||||
#define RP5BA 0x0178 /* 64bit */
|
||||
#define RP6D 0x0180 /* 32bit */
|
||||
#define RP6BA 0x0188 /* 64bit */
|
||||
|
||||
#define ILCL 0x01a0 /* 32bit */
|
||||
#define LCAP 0x01a4 /* 32bit */
|
||||
#define LCTL 0x01a8 /* 16bit */
|
||||
#define LSTS 0x01aa /* 16bit */
|
||||
|
||||
#define RPC 0x0224 /* 32bit */
|
||||
#define RPFN 0x0238 /* 32bit */
|
||||
|
||||
#define TRSR 0x1e00 /* 8bit */
|
||||
#define TRCR 0x1e10 /* 64bit */
|
||||
#define TWDR 0x1e18 /* 64bit */
|
||||
|
||||
#define IOTR0 0x1e80 /* 64bit */
|
||||
#define IOTR1 0x1e88 /* 64bit */
|
||||
#define IOTR2 0x1e90 /* 64bit */
|
||||
#define IOTR3 0x1e98 /* 64bit */
|
||||
|
||||
#define TCTL 0x3000 /* 8bit */
|
||||
|
||||
#define D31IP 0x3100 /* 32bit */
|
||||
#define D30IP 0x3104 /* 32bit */
|
||||
#define D29IP 0x3108 /* 32bit */
|
||||
#define D28IP 0x310c /* 32bit */
|
||||
#define D27IP 0x3110 /* 32bit */
|
||||
#define D31IR 0x3140 /* 16bit */
|
||||
#define D30IR 0x3142 /* 16bit */
|
||||
#define D29IR 0x3144 /* 16bit */
|
||||
#define D28IR 0x3146 /* 16bit */
|
||||
#define D27IR 0x3148 /* 16bit */
|
||||
#define OIC 0x31ff /* 8bit */
|
||||
|
||||
#define RC 0x3400 /* 32bit */
|
||||
#define HPTC 0x3404 /* 32bit */
|
||||
#define GCS 0x3410 /* 32bit */
|
||||
#define BUC 0x3414 /* 32bit */
|
||||
#define FD 0x3418 /* 32bit */
|
||||
#define CG 0x341c /* 32bit */
|
||||
|
||||
/* Function Disable (FD) register values.
|
||||
* Setting a bit disables the corresponding
|
||||
* feature.
|
||||
* Not all features might be disabled on
|
||||
* all chipsets. Esp. ICH-7U is picky.
|
||||
*/
|
||||
#define FD_PCIE6 (1 << 21)
|
||||
#define FD_PCIE5 (1 << 20)
|
||||
#define FD_PCIE4 (1 << 19)
|
||||
#define FD_PCIE3 (1 << 18)
|
||||
#define FD_PCIE2 (1 << 17)
|
||||
#define FD_PCIE1 (1 << 16)
|
||||
#define FD_EHCI (1 << 15)
|
||||
#define FD_LPCB (1 << 14)
|
||||
|
||||
/* UHCI must be disabled from 4 downwards.
|
||||
* If UHCI controllers get disabled, EHCI
|
||||
* must know about it, too! */
|
||||
#define FD_UHCI4 (1 << 11)
|
||||
#define FD_UHCI34 (1 << 10) | FD_UHCI4
|
||||
#define FD_UHCI234 (1 << 9) | FD_UHCI3
|
||||
#define FD_UHCI1234 (1 << 8) | FD_UHCI2
|
||||
|
||||
#define FD_INTLAN (1 << 7)
|
||||
#define FD_ACMOD (1 << 6)
|
||||
#define FD_ACAUD (1 << 5)
|
||||
#define FD_HDAUD (1 << 4)
|
||||
#define FD_SMBUS (1 << 3)
|
||||
#define FD_SATA (1 << 2)
|
||||
#define FD_PATA (1 << 1)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,283 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2008 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
#include <stdint.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/hypertransport.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <bitops.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include "chip.h"
|
||||
#include "i945.h"
|
||||
|
||||
static void ram_resource(device_t dev, unsigned long index, unsigned long basek,
|
||||
unsigned long sizek)
|
||||
{
|
||||
struct resource *resource;
|
||||
|
||||
resource = new_resource(dev, index);
|
||||
resource->base = ((resource_t) basek) << 10;
|
||||
resource->size = ((resource_t) sizek) << 10;
|
||||
resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE |
|
||||
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
|
||||
}
|
||||
|
||||
static void pci_domain_read_resources(device_t dev)
|
||||
{
|
||||
struct resource *resource;
|
||||
|
||||
/* Initialize the system wide io space constraints */
|
||||
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
|
||||
resource->base = 0;
|
||||
resource->size = 0;
|
||||
resource->align = 0;
|
||||
resource->gran = 0;
|
||||
resource->limit = 0xffffUL;
|
||||
resource->flags =
|
||||
IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
|
||||
|
||||
/* Initialize the system wide memory resources constraints */
|
||||
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
|
||||
resource->base = 0;
|
||||
resource->size = 0;
|
||||
resource->align = 0;
|
||||
resource->gran = 0;
|
||||
resource->limit = 0xffffffffUL;
|
||||
resource->flags =
|
||||
IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
|
||||
}
|
||||
|
||||
static void tolm_test(void *gp, struct device *dev, struct resource *new)
|
||||
{
|
||||
struct resource **best_p = gp;
|
||||
struct resource *best;
|
||||
best = *best_p;
|
||||
if (!best || (best->base > new->base)) {
|
||||
best = new;
|
||||
}
|
||||
*best_p = best;
|
||||
}
|
||||
|
||||
static uint32_t find_pci_tolm(struct bus *bus)
|
||||
{
|
||||
struct resource *min;
|
||||
uint32_t tolm;
|
||||
min = 0;
|
||||
search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test,
|
||||
&min);
|
||||
tolm = 0xffffffffUL;
|
||||
if (min && tolm > min->base) {
|
||||
tolm = min->base;
|
||||
}
|
||||
return tolm;
|
||||
}
|
||||
|
||||
static void pci_domain_set_resources(device_t dev)
|
||||
{
|
||||
uint32_t pci_tolm;
|
||||
uint8_t tolud, reg8;
|
||||
uint16_t reg16;
|
||||
unsigned long long tomk, tolmk;
|
||||
|
||||
pci_tolm = find_pci_tolm(&dev->link[0]);
|
||||
|
||||
printk_spew("Base of stolen memory: 0x%08x\n",
|
||||
pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c));
|
||||
|
||||
tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9c);
|
||||
printk_spew("Top of Low Used DRAM: 0x%08x\n", tolud << 24);
|
||||
|
||||
tomk = tolud << 14;
|
||||
|
||||
/* Note: subtract IGD device and TSEG */
|
||||
reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e);
|
||||
if (reg8 & 1) {
|
||||
int tseg_size = 0;
|
||||
printk_debug("TSEG decoded, subtracting ");
|
||||
reg8 >>= 1;
|
||||
reg8 &= 3;
|
||||
switch (reg8) {
|
||||
case 0:
|
||||
tseg_size = 1024;
|
||||
break;
|
||||
case 1:
|
||||
tseg_size = 2048;
|
||||
break;
|
||||
case 2:
|
||||
tseg_size = 8192;
|
||||
break;
|
||||
}
|
||||
|
||||
printk_debug("%dM\n", tseg_size >> 10);
|
||||
tomk -= tseg_size;
|
||||
}
|
||||
|
||||
reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
|
||||
if (!(reg16 & 2)) {
|
||||
int uma_size = 0;
|
||||
printk_debug("IGD decoded, subtracting ");
|
||||
reg16 >>= 4;
|
||||
reg16 &= 7;
|
||||
switch (reg16) {
|
||||
case 1:
|
||||
uma_size = 1024;
|
||||
break;
|
||||
case 3:
|
||||
uma_size = 8192;
|
||||
break;
|
||||
}
|
||||
|
||||
printk_debug("%dM UMA\n", uma_size >> 10);
|
||||
tomk -= uma_size;
|
||||
}
|
||||
|
||||
/* The following needs to be 2 lines, otherwise the second
|
||||
* number is always 0
|
||||
*/
|
||||
printk_info("Available memory: %dK", tomk);
|
||||
printk_info(" (%dM)\n", (tomk >> 10));
|
||||
|
||||
tolmk = tomk;
|
||||
|
||||
/* Report the memory regions */
|
||||
ram_resource(dev, 3, 0, 640);
|
||||
ram_resource(dev, 4, 768, (tolmk - 768));
|
||||
if (tomk > 4 * 1024 * 1024) {
|
||||
ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024);
|
||||
}
|
||||
|
||||
assign_resources(&dev->link[0]);
|
||||
}
|
||||
|
||||
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
|
||||
{
|
||||
max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
|
||||
/* TODO We could determine how many PCIe busses we need in
|
||||
* the bar. For now that number is hardcoded to a max of 64.
|
||||
*/
|
||||
return max;
|
||||
}
|
||||
|
||||
static struct device_operations pci_domain_ops = {
|
||||
.read_resources = pci_domain_read_resources,
|
||||
.set_resources = pci_domain_set_resources,
|
||||
.enable_resources = enable_childrens_resources,
|
||||
.init = 0,
|
||||
.scan_bus = pci_domain_scan_bus,
|
||||
.ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
|
||||
};
|
||||
|
||||
static void mc_read_resources(device_t dev)
|
||||
{
|
||||
struct resource *resource;
|
||||
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
/* So, this is one of the big mysteries in the coreboot resource
|
||||
* allocator. This resource should make sure that the address space
|
||||
* of the PCIe memory mapped config space bar. But it does not.
|
||||
*/
|
||||
|
||||
/* We use 0xcf as an unused index for our PCIe bar so that we find it again */
|
||||
resource = new_resource(dev, 0xcf);
|
||||
resource->base = DEFAULT_PCIEXBAR;
|
||||
resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */
|
||||
resource->flags =
|
||||
IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
|
||||
IORESOURCE_ASSIGNED;
|
||||
printk_debug("Adding PCIe enhanced config space BAR 0x%08x-0x%08x.\n",
|
||||
resource->base, (resource->base + resource->size));
|
||||
}
|
||||
|
||||
static void mc_set_resources(device_t dev)
|
||||
{
|
||||
struct resource *resource, *last;
|
||||
|
||||
/* Report the PCIe BAR */
|
||||
last = &dev->resource[dev->resources];
|
||||
resource = find_resource(dev, 0xcf);
|
||||
if (resource) {
|
||||
report_resource_stored(dev, resource, "<mmconfig>");
|
||||
}
|
||||
|
||||
/* And call the normal set_resources */
|
||||
pci_dev_set_resources(dev);
|
||||
}
|
||||
|
||||
static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
|
||||
{
|
||||
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
|
||||
((device & 0xffff) << 16) | (vendor & 0xffff));
|
||||
}
|
||||
|
||||
static struct pci_operations intel_pci_ops = {
|
||||
.set_subsystem = intel_set_subsystem,
|
||||
};
|
||||
|
||||
static struct device_operations mc_ops = {
|
||||
.read_resources = mc_read_resources,
|
||||
.set_resources = mc_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = 0,
|
||||
.scan_bus = 0,
|
||||
.ops_pci = &intel_pci_ops,
|
||||
};
|
||||
|
||||
static const struct pci_driver mc_driver __pci_driver = {
|
||||
.ops = &mc_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = 0x27a0,
|
||||
};
|
||||
|
||||
static void cpu_bus_init(device_t dev)
|
||||
{
|
||||
initialize_cpus(&dev->link[0]);
|
||||
}
|
||||
|
||||
static void cpu_bus_noop(device_t dev)
|
||||
{
|
||||
}
|
||||
|
||||
static struct device_operations cpu_bus_ops = {
|
||||
.read_resources = cpu_bus_noop,
|
||||
.set_resources = cpu_bus_noop,
|
||||
.enable_resources = cpu_bus_noop,
|
||||
.init = cpu_bus_init,
|
||||
.scan_bus = 0,
|
||||
};
|
||||
|
||||
static void enable_dev(device_t dev)
|
||||
{
|
||||
/* Set the operations if it is a special bus type */
|
||||
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
|
||||
dev->ops = &pci_domain_ops;
|
||||
} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
|
||||
dev->ops = &cpu_bus_ops;
|
||||
}
|
||||
}
|
||||
|
||||
struct chip_operations northbridge_intel_i945_ops = {
|
||||
CHIP_NAME("Intel i945 Northbridge")
|
||||
.enable_dev = enable_dev,
|
||||
};
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2008 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include "i945.h"
|
||||
|
||||
static inline __attribute__ ((always_inline))
|
||||
u8 pcie_read_config8(device_t dev, unsigned int where)
|
||||
{
|
||||
unsigned long addr;
|
||||
addr = DEFAULT_PCIEXBAR | dev | where;
|
||||
return read8(addr);
|
||||
}
|
||||
|
||||
static inline __attribute__ ((always_inline))
|
||||
u16 pcie_read_config16(device_t dev, unsigned int where)
|
||||
{
|
||||
unsigned long addr;
|
||||
addr = DEFAULT_PCIEXBAR | dev | where;
|
||||
return read16(addr);
|
||||
}
|
||||
|
||||
static inline __attribute__ ((always_inline))
|
||||
u32 pcie_read_config32(device_t dev, unsigned int where)
|
||||
{
|
||||
unsigned long addr;
|
||||
addr = DEFAULT_PCIEXBAR | dev | where;
|
||||
return read32(addr);
|
||||
}
|
||||
|
||||
static inline __attribute__ ((always_inline))
|
||||
void pcie_write_config8(device_t dev, unsigned int where, u8 value)
|
||||
{
|
||||
unsigned long addr;
|
||||
addr = DEFAULT_PCIEXBAR | dev | where;
|
||||
write8(addr, value);
|
||||
}
|
||||
|
||||
static inline __attribute__ ((always_inline))
|
||||
void pcie_write_config16(device_t dev, unsigned int where, u16 value)
|
||||
{
|
||||
unsigned long addr;
|
||||
addr = DEFAULT_PCIEXBAR | dev | where;
|
||||
write16(addr, value);
|
||||
}
|
||||
|
||||
static inline __attribute__ ((always_inline))
|
||||
void pcie_write_config32(device_t dev, unsigned int where, u32 value)
|
||||
{
|
||||
unsigned long addr;
|
||||
addr = DEFAULT_PCIEXBAR | dev | where;
|
||||
write32(addr, value);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2008 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef RAMINIT_H
|
||||
#define RAMINIT_H
|
||||
|
||||
#define DIMM_SOCKETS 2
|
||||
|
||||
#define DIMM_SPD_BASE 0x50
|
||||
#define DIMM_TCO_BASE 0x30
|
||||
|
||||
/* Burst length is always 8 */
|
||||
#define BURSTLENGTH 8
|
||||
|
||||
struct sys_info {
|
||||
u16 memory_frequency; /* 400, 533 or 667 */
|
||||
u16 fsb_frequency; /* 400, 533 or 667 */
|
||||
|
||||
u8 trp; /* calculated by sdram_detect_smallest_tRP() */
|
||||
u8 trcd; /* calculated by sdram_detect_smallest_tRCD() */
|
||||
u8 tras; /* calculated by sdram_detect_smallest_tRAS() */
|
||||
u8 trfc; /* calculated by sdram_detect_smallest_tRFC() */
|
||||
u8 twr; /* calculated by sdram_detect_smallest_tWR() */
|
||||
|
||||
u8 cas; /* 3, 4 or 5 */
|
||||
u8 refresh; /* 0 = 15.6us, 1 = 7.8us */
|
||||
|
||||
u8 dual_channel; /* 0 or 1 */
|
||||
u8 interleaved;
|
||||
|
||||
u8 mvco4x; /* 0 (8x) or 1 (4x) */
|
||||
u8 clkcfg_bit7;
|
||||
u8 boot_path;
|
||||
|
||||
u8 package; /* 0 = planar, 1 = stacked */
|
||||
#define SYSINFO_PACKAGE_PLANAR 0x00
|
||||
#define SYSINFO_PACKAGE_STACKED 0x01
|
||||
u8 dimm[2 * DIMM_SOCKETS];
|
||||
#define SYSINFO_DIMM_X16DS 0x00
|
||||
#define SYSINFO_DIMM_X8DS 0x01
|
||||
#define SYSINFO_DIMM_X16SS 0x02
|
||||
#define SYSINFO_DIMM_X8DDS 0x03
|
||||
#define SYSINFO_DIMM_NOT_POPULATED 0x04
|
||||
|
||||
u8 banks[2 * DIMM_SOCKETS];
|
||||
|
||||
u8 banksize[2 * 2 * DIMM_SOCKETS];
|
||||
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#endif /* RAMINIT_H */
|
||||
|
|
@ -0,0 +1,338 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2008 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include "raminit.h"
|
||||
|
||||
/**
|
||||
* sample the strobes signal
|
||||
*/
|
||||
static u32 sample_strobes(int channel_offset, struct sys_info *sysinfo)
|
||||
{
|
||||
u32 reg32, addr;
|
||||
int i;
|
||||
|
||||
MCHBAR32(C0DRC1 + channel_offset) |= (1 << 6);
|
||||
|
||||
MCHBAR32(C0DRC1 + channel_offset) &= ~(1 << 6);
|
||||
|
||||
addr = 0;
|
||||
|
||||
if (channel_offset != 0) { /* must be dual channel */
|
||||
if (sysinfo->interleaved == 1) {
|
||||
addr |= (1 << 6);
|
||||
} else {
|
||||
addr = ((u32)MCHBAR8(C0DRB3)) << 25;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < 28; i++) {
|
||||
read32(addr);
|
||||
read32(addr + 0x80);
|
||||
}
|
||||
|
||||
reg32 = MCHBAR32(RCVENMT);
|
||||
if (channel_offset == 0) {
|
||||
reg32 = reg32 << 2;
|
||||
}
|
||||
|
||||
/**
|
||||
* [19] = 1: all bits are high
|
||||
* [18] = 1: all bits are low
|
||||
* [19:18] = 00: bits are mixed high, low
|
||||
*/
|
||||
return reg32;
|
||||
}
|
||||
|
||||
/**
|
||||
* This function sets receive enable coarse and medium timing parameters
|
||||
*/
|
||||
|
||||
static void set_receive_enable(int channel_offset, u8 medium, u8 coarse)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
printk_spew(" set_receive_enable() medium=0x%x, coarse=0x%x\r\n", medium, coarse);
|
||||
|
||||
reg32 = MCHBAR32(C0DRT1 + channel_offset);
|
||||
reg32 &= 0xf0ffffff;
|
||||
reg32 |= ((u32)coarse & 0x0f) << 24;
|
||||
MCHBAR32(C0DRT1 + channel_offset) = reg32;
|
||||
|
||||
if (coarse > 0x0f)
|
||||
printk_debug("set_receive_enable: coarse overflow: 0x%02x.\n", coarse);
|
||||
|
||||
/* medium control
|
||||
*
|
||||
* 00 - 1/4 clock
|
||||
* 01 - 1/2 clock
|
||||
* 10 - 3/4 clock
|
||||
* 11 - 1 clock
|
||||
*/
|
||||
|
||||
reg32 = MCHBAR32(RCVENMT);
|
||||
if (!channel_offset) {
|
||||
|
||||
reg32 &= ~(3 << 2);
|
||||
reg32 |= medium << 2;
|
||||
} else {
|
||||
|
||||
reg32 &= ~(3 << 0);
|
||||
reg32 |= medium;
|
||||
}
|
||||
MCHBAR32(RCVENMT) = reg32;
|
||||
|
||||
}
|
||||
|
||||
static int normalize(int channel_offset, u8 * mediumcoarse, u8 * fine)
|
||||
{
|
||||
printk_spew(" normalize()\r\n");
|
||||
|
||||
if (*fine < 0x80)
|
||||
return 0;
|
||||
|
||||
*fine -= 0x80;
|
||||
*mediumcoarse += 1;
|
||||
|
||||
if (*mediumcoarse >= 0x40) {
|
||||
printk_debug("Normalize Error\r\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
set_receive_enable(channel_offset, *mediumcoarse & 3,
|
||||
*mediumcoarse >> 2);
|
||||
|
||||
MCHBAR8(C0WL0REOST + channel_offset) = *fine;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int find_preamble(int channel_offset, u8 * mediumcoarse,
|
||||
struct sys_info *sysinfo)
|
||||
{
|
||||
/* find start of the data phase */
|
||||
u32 reg32;
|
||||
|
||||
printk_spew(" find_preamble()\r\n");
|
||||
|
||||
do {
|
||||
if (*mediumcoarse < 4) {
|
||||
|
||||
printk_debug("No Preamble found.\r\n");
|
||||
return -1;
|
||||
}
|
||||
*mediumcoarse -= 4;
|
||||
|
||||
set_receive_enable(channel_offset, *mediumcoarse & 3,
|
||||
*mediumcoarse >> 2);
|
||||
|
||||
reg32 = sample_strobes(channel_offset, sysinfo);
|
||||
|
||||
} while (reg32 & (1 << 19));
|
||||
|
||||
if (!(reg32 & (1 << 18))) {
|
||||
|
||||
printk_debug("No Preamble found (neither high nor low).\r\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* add a quarter clock to the current receive enable settings
|
||||
*/
|
||||
|
||||
static int add_quarter_clock(int channel_offset, u8 * mediumcoarse, u8 * fine)
|
||||
{
|
||||
printk_spew(" add_quarter_clock() mediumcoarse=%02x fine=%02x\r\n",
|
||||
*mediumcoarse, *fine);
|
||||
if (*fine >= 0x80) {
|
||||
*fine -= 0x80;
|
||||
|
||||
*mediumcoarse += 2;
|
||||
if (*mediumcoarse >= 0x40) {
|
||||
printk_debug("clocks at max.\r\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
set_receive_enable(channel_offset, *mediumcoarse & 3,
|
||||
*mediumcoarse >> 2);
|
||||
} else {
|
||||
*fine += 0x80;
|
||||
}
|
||||
|
||||
MCHBAR8(C0WL0REOST + channel_offset) = *fine;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int find_strobes_low(int channel_offset, u8 * mediumcoarse, u8 * fine,
|
||||
struct sys_info *sysinfo)
|
||||
{
|
||||
u32 rcvenmt;
|
||||
|
||||
printk_spew(" find_strobes_low()\r\n");
|
||||
|
||||
for (;;) {
|
||||
MCHBAR8(C0WL0REOST + channel_offset) = *fine;
|
||||
|
||||
set_receive_enable(channel_offset, *mediumcoarse & 3,
|
||||
*mediumcoarse >> 2);
|
||||
|
||||
rcvenmt = sample_strobes(channel_offset, sysinfo);
|
||||
|
||||
if (((rcvenmt & (1 << 18)) != 0))
|
||||
return 0;
|
||||
|
||||
|
||||
*fine -= 0x80;
|
||||
if (*fine == 0)
|
||||
continue;
|
||||
|
||||
*mediumcoarse -= 2;
|
||||
if (*mediumcoarse < 0xfe)
|
||||
continue;
|
||||
|
||||
break;
|
||||
|
||||
}
|
||||
|
||||
printk_debug("Could not find low strobe\r\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int find_strobes_edge(int channel_offset, u8 * mediumcoarse, u8 * fine,
|
||||
struct sys_info *sysinfo)
|
||||
{
|
||||
int counter;
|
||||
u32 rcvenmt;
|
||||
|
||||
printk_spew(" find_strobes_edge()\r\n");
|
||||
|
||||
counter = 8;
|
||||
set_receive_enable(channel_offset, *mediumcoarse & 3,
|
||||
*mediumcoarse >> 2);
|
||||
|
||||
for (;;) {
|
||||
MCHBAR8(C0WL0REOST + channel_offset) = *fine;
|
||||
rcvenmt = sample_strobes(channel_offset, sysinfo);
|
||||
|
||||
if ((rcvenmt & (1 << 19)) == 0) {
|
||||
counter = 8;
|
||||
} else {
|
||||
counter--;
|
||||
if (!counter)
|
||||
break;
|
||||
}
|
||||
|
||||
*fine = *fine + 1;
|
||||
if (*fine < 0xf8) {
|
||||
if (*fine & (1 << 3)) {
|
||||
*fine &= ~(1 << 3);
|
||||
*fine += 0x10;
|
||||
}
|
||||
continue;
|
||||
}
|
||||
|
||||
*fine = 0;
|
||||
*mediumcoarse += 2;
|
||||
if (*mediumcoarse <= 0x40) {
|
||||
set_receive_enable(channel_offset, *mediumcoarse & 3,
|
||||
*mediumcoarse >> 2);
|
||||
continue;
|
||||
}
|
||||
|
||||
printk_debug("could not find rising edge.\r\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
*fine -= 7;
|
||||
if (*fine >= 0xf9) {
|
||||
*mediumcoarse -= 2;
|
||||
set_receive_enable(channel_offset, *mediumcoarse & 3,
|
||||
*mediumcoarse >> 2);
|
||||
}
|
||||
|
||||
*fine &= ~(1 << 3);
|
||||
MCHBAR8(C0WL0REOST + channel_offset) = *fine;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Here we use a trick. The RCVEN channel 0 registers are all at an
|
||||
* offset of 0x80 to the channel 0 registers. We don't want to waste
|
||||
* a lot of if()s so let's just pass 0 or 0x80 for the channel offset.
|
||||
*/
|
||||
|
||||
static int receive_enable_autoconfig(int channel_offset,
|
||||
struct sys_info *sysinfo)
|
||||
{
|
||||
u8 mediumcoarse;
|
||||
u8 fine;
|
||||
|
||||
printk_spew("receive_enable_autoconfig() for channel %d\r\n",
|
||||
channel_offset ? 1 : 0);
|
||||
|
||||
/* Set initial values */
|
||||
mediumcoarse = (sysinfo->cas << 2) | 3;
|
||||
fine = 0;
|
||||
|
||||
if (find_strobes_low(channel_offset, &mediumcoarse, &fine, sysinfo))
|
||||
return -1;
|
||||
|
||||
if (find_strobes_edge(channel_offset, &mediumcoarse, &fine, sysinfo))
|
||||
return -1;
|
||||
|
||||
if (add_quarter_clock(channel_offset, &mediumcoarse, &fine))
|
||||
return -1;
|
||||
|
||||
if (find_preamble(channel_offset, &mediumcoarse, sysinfo))
|
||||
return -1;
|
||||
|
||||
if (add_quarter_clock(channel_offset, &mediumcoarse, &fine))
|
||||
return -1;
|
||||
|
||||
if (normalize(channel_offset, &mediumcoarse, &fine))
|
||||
return -1;
|
||||
|
||||
/* This is a debug check to see if the rcven code is fully working.
|
||||
* It can be removed when the output message is not printed anymore
|
||||
*/
|
||||
if (MCHBAR8(C0WL0REOST + channel_offset) == 0) {
|
||||
printk_debug("Weird. No C%sWL0REOST\n", channel_offset?"1":"0");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void receive_enable_adjust(struct sys_info *sysinfo)
|
||||
{
|
||||
/* Is channel 0 populated? */
|
||||
if (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED
|
||||
|| sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)
|
||||
if (receive_enable_autoconfig(0, sysinfo))
|
||||
return;
|
||||
|
||||
/* Is channel 1 populated? */
|
||||
if (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED
|
||||
|| sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)
|
||||
if (receive_enable_autoconfig(0x80, sysinfo))
|
||||
return;
|
||||
}
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2008 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
static int bios_reset_detected(void)
|
||||
{
|
||||
/* For now ...
|
||||
* DO NOT, I repeat, DO NOT remove this. If you don't like the
|
||||
* situation, implement this instead.
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2008 coresystems GmbH
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <cpu/x86/tsc.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
|
||||
/**
|
||||
* Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
|
||||
*/
|
||||
|
||||
static void udelay(u32 us)
|
||||
{
|
||||
u32 dword;
|
||||
tsc_t tsc, tsc1, tscd;
|
||||
msr_t msr;
|
||||
u32 fsb = 0, divisor;
|
||||
u32 d;
|
||||
u32 dn = 0x1000000 / 2;
|
||||
|
||||
msr = rdmsr(0xcd);
|
||||
switch (msr.lo & 0x07) {
|
||||
case 5:
|
||||
fsb = 400;
|
||||
break;
|
||||
case 1:
|
||||
fsb = 533;
|
||||
break;
|
||||
case 3:
|
||||
fsb = 667;
|
||||
break;
|
||||
}
|
||||
|
||||
msr = rdmsr(0x198);
|
||||
divisor = (msr.hi >> 8) & 0x1f;
|
||||
|
||||
d = fsb * divisor;
|
||||
|
||||
tscd.hi = us / dn;
|
||||
tscd.lo = (us - tscd.hi * dn) * d;
|
||||
|
||||
tsc1 = rdtsc();
|
||||
dword = tsc1.lo + tscd.lo;
|
||||
if ((dword < tsc1.lo) || (dword < tscd.lo)) {
|
||||
tsc1.hi++;
|
||||
}
|
||||
tsc1.lo = dword;
|
||||
tsc1.hi += tscd.hi;
|
||||
|
||||
do {
|
||||
tsc = rdtsc();
|
||||
} while ((tsc.hi > tsc1.hi)
|
||||
|| ((tsc.hi == tsc1.hi) && (tsc.lo > tsc1.lo)));
|
||||
|
||||
}
|
||||
Loading…
Reference in New Issue