device/dram/ddr2.c: Improve error returning and debug output
This patch outputs decoding errors with BIOS_WARNING instead of depending on CONFIG_DEBUG_RAM_SETUP. Returns SPD_STATUS_INVALID on invalid settings for tRR, bcd and tCK and doesn't try to create a valid setting if an invalid setting is detected. Change-Id: Iee434d1fa1a9d911cc3683b88b260881ed6434ea Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans
Martin Roth
parent
0ab4904481
commit
2785c118a6
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@ -113,7 +113,7 @@ u8 spd_get_msbs(u8 c)
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* Decodes a raw SPD data from a DDR2 DIMM.
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* Returns cycle time in 1/256th ns.
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*/
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static u32 spd_decode_tck_time(u8 c)
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static int spd_decode_tck_time(u32 *tck, u8 c)
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{
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u8 high, low;
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@ -132,11 +132,17 @@ static u32 spd_decode_tck_time(u8 c)
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case 0xd:
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low = 75;
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break;
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case 0xe:
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case 0xf:
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printk(BIOS_WARNING, "Invalid tck setting. "
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"lower nibble is 0x%x\n", c & 0xf);
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return CB_ERR;
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default:
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low = (c & 0xf) * 10;
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}
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return ((high * 100 + low) << 8) / 100;
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*tck = ((high * 100 + low) << 8) / 100;
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return CB_SUCCESS;
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}
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/**
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@ -145,14 +151,17 @@ static u32 spd_decode_tck_time(u8 c)
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* Decodes a raw SPD data from a DDR2 DIMM.
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* Returns cycle time in 1/256th ns.
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*/
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static u32 spd_decode_bcd_time(u8 c)
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static int spd_decode_bcd_time(u32 *bcd, u8 c)
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{
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u8 high, low;
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high = c >> 4;
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low = c & 0xf;
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if (high >= 10 || low >= 10)
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return CB_ERR;
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return ((high * 10 + low) << 8) / 100;
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*bcd = ((high * 10 + low) << 8) / 100;
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return CB_SUCCESS;
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}
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/**
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@ -177,26 +186,26 @@ static u32 spd_decode_quarter_time(u8 c)
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* Decodes a raw SPD data from a DDR2 DIMM.
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* Returns cycle time in 1/256th us.
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*/
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static u32 spd_decode_tRR_time(u8 c)
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static int spd_decode_tRR_time(u32 *tRR, u8 c)
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{
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switch (c) {
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default:
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printk(BIOS_WARNING,
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"Unknown tRR value, using default of 15.6us.");
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/* Fallthrough */
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printk(BIOS_WARNING, "Invalid tRR value 0x%x\n", c);
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return CB_ERR;
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case 0x80:
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return 15625 << 8;
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*tRR = 15625 << 8;
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case 0x81:
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return 15625 << 6;
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*tRR = 15625 << 6;
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case 0x82:
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return 15625 << 7;
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*tRR = 15625 << 7;
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case 0x83:
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return 15625 << 9;
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*tRR = 15625 << 9;
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case 0x84:
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return 15625 << 10;
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*tRR = 15625 << 10;
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case 0x85:
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return 15625 << 11;
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*tRR = 15625 << 11;
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}
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return CB_SUCCESS;
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}
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/**
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@ -297,20 +306,21 @@ int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])
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printram("SPD contains 0x%02x bytes\n", spd_size);
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if (spd_size < 64 || eeprom_size < 64) {
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printram("ERROR: SPD to small\n");
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printk(BIOS_WARNING, "ERROR: SPD to small\n");
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dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED;
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return SPD_STATUS_INVALID;
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}
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if (spd_ddr2_calc_checksum(spd, spd_size) != spd[63]) {
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printram("ERROR: SPD checksum error\n");
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printk(BIOS_WARNING, "ERROR: SPD checksum error\n");
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dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED;
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return SPD_STATUS_CRC_ERROR;
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}
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reg8 = spd[62];
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if ((reg8 & 0xf0) != 0x10) {
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printram("ERROR: Unsupported SPD revision %01x.%01x\n",
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printk(BIOS_WARNING,
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"ERROR: Unsupported SPD revision %01x.%01x\n",
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reg8 >> 4, reg8 & 0xf);
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dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED;
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return SPD_STATUS_INVALID;
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@ -321,7 +331,7 @@ int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])
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reg8 = spd[2];
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printram(" Type : 0x%02x\n", reg8);
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if (reg8 != 0x08) {
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printram("ERROR: Unsupported SPD type %x\n", reg8);
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printk(BIOS_WARNING, "ERROR: Unsupported SPD type %x\n", reg8);
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dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED;
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return SPD_STATUS_INVALID;
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}
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@ -331,14 +341,16 @@ int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])
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printram(" Rows : %u\n", dimm->row_bits);
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if ((dimm->row_bits > 31) ||
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((dimm->row_bits > 15) && (dimm->rev < 0x13))) {
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printram(" Invalid number of memory rows\n");
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printk(BIOS_WARNING,
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"SPD decode: invalid number of memory rows\n");
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ret = SPD_STATUS_INVALID_FIELD;
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}
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dimm->col_bits = spd[4];
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printram(" Columns : %u\n", dimm->col_bits);
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if (dimm->col_bits > 15) {
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printram(" Invalid number of memory columns\n");
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printk(BIOS_WARNING,
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"SPD decode: invalid number of memory columns\n");
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ret = SPD_STATUS_INVALID_FIELD;
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}
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@ -348,21 +360,22 @@ int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])
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dimm->mod_width = spd[6];
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printram(" Module data width : x%u\n", dimm->mod_width);
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if (!dimm->mod_width) {
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printram(" Invalid module data width\n");
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printk(BIOS_WARNING, "SPD decode: invalid module data width\n");
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ret = SPD_STATUS_INVALID_FIELD;
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}
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dimm->width = spd[13];
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printram(" SDRAM width : x%u\n", dimm->width);
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if (!dimm->width) {
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printram(" Invalid SDRAM width\n");
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printk(BIOS_WARNING, "SPD decode: invalid SDRAM width\n");
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ret = SPD_STATUS_INVALID_FIELD;
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}
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dimm->banks = spd[17];
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printram(" Banks : %u\n", dimm->banks);
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if (!dimm->banks) {
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printram(" Invalid module banks count\n");
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printk(BIOS_WARNING,
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"SPD decode: invalid module banks count\n");
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ret = SPD_STATUS_INVALID_FIELD;
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}
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@ -392,23 +405,26 @@ int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])
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printram(" Voltage : 1.8V\n");
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break;
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default:
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printram(" Unknown voltage level.\n");
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printk(BIOS_WARNING, "SPD decode: unknown voltage level.\n");
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ret = SPD_STATUS_INVALID_FIELD;
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}
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dimm->cas_supported = spd[18];
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if ((dimm->cas_supported & 0x3) || !dimm->cas_supported) {
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printram(" Invalid CAS support advertised.\n");
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printk(BIOS_WARNING,
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"SPD decode: invalid CAS support advertised.\n");
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ret = SPD_STATUS_INVALID_FIELD;
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}
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printram(" Supported CAS mask : 0x%x\n", dimm->cas_supported);
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if ((dimm->rev < 0x13) && (dimm->cas_supported & 0x80)) {
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printram(" Invalid CAS support advertised.\n");
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printk(BIOS_WARNING,
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"SPD decode: invalid CAS support advertised.\n");
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ret = SPD_STATUS_INVALID_FIELD;
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}
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if ((dimm->rev < 0x12) && (dimm->cas_supported & 0x40)) {
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printram(" Invalid CAS support advertised.\n");
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printk(BIOS_WARNING,
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"SPD decode: invalid CAS support advertised.\n");
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ret = SPD_STATUS_INVALID_FIELD;
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}
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@ -416,26 +432,60 @@ int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])
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cl = spd_get_msbs(dimm->cas_supported);
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/* SDRAM Cycle time at Maximum Supported CAS Latency (CL), CL=X */
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dimm->cycle_time[cl] = spd_decode_tck_time(spd[9]);
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if (spd_decode_tck_time(&dimm->cycle_time[cl], spd[9]) != CB_SUCCESS) {
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printk(BIOS_WARNING,
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"SPD decode: invalid min tCL for CAS%d\n", cl);
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ret = SPD_STATUS_INVALID_FIELD;
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}
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/* SDRAM Access from Clock */
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dimm->access_time[cl] = spd_decode_bcd_time(spd[10]);
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if (spd_decode_bcd_time(&dimm->access_time[cl], spd[10])
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!= CB_SUCCESS) {
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printk(BIOS_WARNING,
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"SPD decode: invalid min tAC for CAS%d\n", cl);
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ret = SPD_STATUS_INVALID_FIELD;
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}
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if (dimm->cas_supported & (1 << (cl - 1))) {
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/* Minimum Clock Cycle at CLX-1 */
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dimm->cycle_time[cl - 1] = spd_decode_tck_time(spd[23]);
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if (spd_decode_tck_time(&dimm->cycle_time[cl - 1], spd[23])
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!= CB_SUCCESS) {
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printk(BIOS_WARNING,
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"SPD decode: invalid min tCL for CAS%d\n",
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cl - 1);
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ret = SPD_STATUS_INVALID_FIELD;
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}
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/* Maximum Data Access Time (tAC) from Clock at CLX-1 */
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dimm->access_time[cl - 1] = spd_decode_bcd_time(spd[24]);
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if (spd_decode_bcd_time(&dimm->access_time[cl - 1], spd[24])
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!= CB_SUCCESS) {
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printk(BIOS_WARNING,
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"SPD decode: invalid min tAC for CAS%d\n",
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cl - 1);
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ret = SPD_STATUS_INVALID_FIELD;
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}
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}
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if (dimm->cas_supported & (1 << (cl - 2))) {
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/* Minimum Clock Cycle at CLX-2 */
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dimm->cycle_time[cl - 2] = spd_decode_tck_time(spd[25]);
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if (spd_decode_tck_time(&dimm->cycle_time[cl - 2], spd[25])
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!= CB_SUCCESS) {
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printk(BIOS_WARNING,
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"SPD decode: invalid min tCL for CAS%d\n",
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cl - 2);
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ret = SPD_STATUS_INVALID_FIELD;
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}
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/* Maximum Data Access Time (tAC) from Clock at CLX-2 */
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dimm->access_time[cl - 2] = spd_decode_bcd_time(spd[26]);
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if (spd_decode_bcd_time(&dimm->access_time[cl - 2], spd[26])
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!= CB_SUCCESS) {
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printk(BIOS_WARNING,
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"SPD decode: invalid min tAC for CAS%d\n",
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cl - 2);
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ret = SPD_STATUS_INVALID_FIELD;
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}
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}
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reg8 = (spd[31] >> 5) | (spd[31] << 3);
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if (!reg8) {
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printram(" Invalid rank density.\n");
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printk(BIOS_WARNING,
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"SPD decode: invalid rank density.\n");
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ret = SPD_STATUS_INVALID_FIELD;
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}
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@ -449,7 +499,10 @@ int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])
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printram(" Capacity : %u GB\n", dimm->size_mb >> 10);
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/* SDRAM Maximum Cycle Time (tCKmax) */
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dimm->tCK = spd_decode_tck_time(spd[43]);
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if (spd_decode_bcd_time(&dimm->tCK, spd[43]) != CB_SUCCESS) {
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printk(BIOS_WARNING, "SPD decode: invalid Max tCK\n");
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ret = SPD_STATUS_INVALID_FIELD;
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}
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/* Minimum Write Recovery Time (tWRmin) */
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dimm->tWR = spd_decode_quarter_time(spd[36]);
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/* Minimum RAS# to CAS# Delay Time (tRCDmin) */
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@ -468,9 +521,15 @@ int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])
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/* Minimum Internal Read to Precharge Command Delay Time (tRTPmin) */
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dimm->tRTP = spd_decode_quarter_time(spd[38]);
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/* Data Input Setup Time Before Strobe */
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dimm->tDS = spd_decode_bcd_time(spd[34]);
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if (spd_decode_bcd_time(&dimm->tDS, spd[34]) != CB_SUCCESS) {
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printk(BIOS_WARNING, "SPD decode: invalid tDS\n");
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ret = SPD_STATUS_INVALID_FIELD;
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}
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/* Data Input Hold Time After Strobe */
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dimm->tDH = spd_decode_bcd_time(spd[35]);
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if (spd_decode_bcd_time(&dimm->tDH, spd[35]) != CB_SUCCESS) {
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printk(BIOS_WARNING, "SPD decode: invalid tDH\n");
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ret = SPD_STATUS_INVALID_FIELD;
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}
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/* SDRAM Device DQS-DQ Skew for DQS and associated DQ signals */
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dimm->tDQSQ = (spd[44] << 8) / 100;
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/* SDRAM Device Maximum Read Data Hold Skew Factor */
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@ -478,7 +537,8 @@ int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2])
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/* PLL Relock Time in us */
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dimm->tPLL = spd[46] << 8;
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/* Refresh rate in us */
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dimm->tRR = spd_decode_tRR_time(spd[12]);
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if (spd_decode_tRR_time(&dimm->tRR, spd[12]) != CB_SUCCESS)
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ret = SPD_STATUS_INVALID_FIELD;
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/* Number of PLLs on DIMM */
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if (dimm->rev >= 0x11)
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