src/soc/intel: Document meaning of variables

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Iaf88f34cedd09e2461bb05050392e178ec84d5d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

src/soc/intel/alderlake/chip.h

@@ -154,8 +154,8 @@ enum ddi_ports {
 };
 
 enum ddi_port_flags {
-	DDI_ENABLE_DDC = 1 << 0,
-	DDI_ENABLE_HPD = 1 << 1,
+	DDI_ENABLE_DDC = 1 << 0, // Display Data Channel
+	DDI_ENABLE_HPD = 1 << 1, // Hot Plug Detect
 };
 
 /*

src/soc/intel/common/block/include/intelblocks/meminit.h

@@ -22,8 +22,8 @@
 
 /* Different memory topologies supported by the platform. */
 enum mem_topology {
-	MEM_TOPO_MEMORY_DOWN = BIT(0),
-	MEM_TOPO_DIMM_MODULE = BIT(1),
+	MEM_TOPO_MEMORY_DOWN = BIT(0), // memory is soldered onto board
+	MEM_TOPO_DIMM_MODULE = BIT(1), // memory is composed of DIMM modules
 	MEM_TOPO_MIXED = MEM_TOPO_MEMORY_DOWN | MEM_TOPO_DIMM_MODULE,
 };
 

src/soc/intel/common/block/include/intelblocks/pcie_rp.h

@@ -15,6 +15,7 @@
 
 enum pcie_rp_flags {
 	PCIE_RP_HOTPLUG = (1 << 0),
+	/* PCIE RP Latency Tolerance Report */
 	PCIE_RP_LTR = (1 << 1),
 	/* PCIE RP Advanced Error Report */
 	PCIE_RP_AER = (1 << 2),

src/soc/intel/meteorlake/chip.h

@@ -51,8 +51,8 @@ enum ddi_ports {
 };
 
 enum ddi_port_flags {
-	DDI_ENABLE_DDC = 1 << 0,
-	DDI_ENABLE_HPD = 1 << 1,
+	DDI_ENABLE_DDC = 1 << 0, // Display Data Channel
+	DDI_ENABLE_HPD = 1 << 1, // Hot Plug Detect
 };
 
 /*