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nb/intel/i945: Remove redundant use of ACPI offset operator 

IASL version 20180927 and greater, detects Unnecessary/redundant uses of
the Offset() operator within a Field Unit list.
It then sends a remark "^ Unnecessary/redundant use of Offset"

example:
    OperationRegion (OPR1, SystemMemory, 0x100, 0x100)
    Field (OPR1)
    {
        Offset (0),     // Never needed
        FLD1, 32,
        Offset (4),     // Redundant, offset is already 4 (bytes)
        FLD2, 8,
        Offset (64),    // OK use of Offset.
        FLD3, 16,
    }

We will have those remarks:
dsdt.asl     14:         Offset (0),
Remark   2158 -                 ^ Unnecessary/redundant use of Offset
operator

dsdt.asl     16:         Offset (4),
Remark   2158 -                 ^ Unnecessary/redundant use of Offset
operator

Change-Id: Ie1f2a2ace335af7984209c9e286b9f85e5342a7e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31671
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2019-03-01 10:45:44 +01:00 committed by Patrick Georgi
parent ee69f73dbf
commit 2796b242b2
1 changed files with 9 additions and 9 deletions
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18
src/northbridge/intel/i945/acpi/hostbridge.asl
View File

@ -34,18 +34,18 @@ Device (MCHC)
, 11, // , 11, //
EPBR, 20, // EPBAR EPBR, 20, // EPBAR
Offset (0x44), // MCHBAR // MCHBAR
MHEN, 1, // Enable MHEN, 1, // Enable
, 13, // , 13, //
MHBR, 18, // MCHBAR MHBR, 18, // MCHBAR
Offset (0x48), // PCIe BAR // PCIe BAR
PXEN, 1, // Enable PXEN, 1, // Enable
PXSZ, 2, // BAR size PXSZ, 2, // BAR size
, 23, // , 23, //
PXBR, 6, // PCIe BAR PXBR, 6, // PCIe BAR
Offset (0x4c), // DMIBAR // DMIBAR
DMEN, 1, // Enable DMEN, 1, // Enable
, 11, // , 11, //
DMBR, 20, // DMIBAR DMBR, 20, // DMIBAR
@ -56,32 +56,32 @@ Device (MCHC)
, 4, , 4,
PM0H, 2, PM0H, 2,
, 2, , 2,
Offset (0x91), // PAM1 // PAM1
PM1L, 2, PM1L, 2,
, 2, , 2,
PM1H, 2, PM1H, 2,
, 2, , 2,
Offset (0x92), // PAM2 // PAM2
PM2L, 2, PM2L, 2,
, 2, , 2,
PM2H, 2, PM2H, 2,
, 2, , 2,
Offset (0x93), // PAM3 // PAM3
PM3L, 2, PM3L, 2,
, 2, , 2,
PM3H, 2, PM3H, 2,
, 2, , 2,
Offset (0x94), // PAM4 // PAM4
PM4L, 2, PM4L, 2,
, 2, , 2,
PM4H, 2, PM4H, 2,
, 2, , 2,
Offset (0x95), // PAM5 // PAM5
PM5L, 2, PM5L, 2,
, 2, , 2,
PM5H, 2, PM5H, 2,
, 2, , 2,
Offset (0x96), // PAM6 // PAM6
PM6L, 2, PM6L, 2,
, 2, , 2,
PM6H, 2, PM6H, 2,