mb/intel/baskingridge: Put GPIOs in a C file

This will allow dropping the pointer inside romstage_params.

Change-Id: I04b695cbe2a6485b42ab037f4f7359a2429c3440
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>

src/mainboard/intel/baskingridge/Makefile.inc

@@ -1,5 +1,7 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+romstage-y += gpio.c
+
 romstage-y += chromeos.c
 ramstage-y += chromeos.c
 verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c

src/mainboard/intel/baskingridge/gpio.c

@@ -1,8 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef BASKING_RIDGE_GPIO_H
-#define BASKING_RIDGE_GPIO_H
-
 #include <southbridge/intel/common/gpio.h>
 
 const struct pch_gpio_set1 pch_gpio_set1_mode = {
@@ -226,5 +223,3 @@ const struct pch_gpio_map mainboard_gpio_map = {
 		.level     = &pch_gpio_set3_level,
 	},
 };
-
-#endif

src/mainboard/intel/baskingridge/romstage.c

@@ -7,7 +7,7 @@
 #include <northbridge/intel/haswell/haswell.h>
 #include <northbridge/intel/haswell/raminit.h>
 #include <southbridge/intel/lynxpoint/pch.h>
-#include "gpio.h"
+#include <southbridge/intel/common/gpio.h>
 
 const struct rcba_config_instruction rcba_config[] = {
 	/*