mb/emulation/qemu-q35: Account for TSEG
TSEG is located below TOLUD. The size is configured in ESMRAMC but can also be configured with "-global mch.extended-tseg-mbytes=5" command line argument. Note that the size in ESMRAMC needs to be 'invalid' (3) for this to take action. coreboot will leave TSEG at the default 1MiB. Note that even if TSEG does not end up being used, it is likely a good idea to not put anything there as if SMM gets locked down by something else it will suddenly be inaccessible. Change-Id: I5fd82a42d6602f1369bb3c69556c46f537542705 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@ -4,6 +4,7 @@
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#include <arch/io.h>
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#include <arch/romstage.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include "memory.h"
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#include "fw_cfg.h"
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@ -50,6 +51,11 @@ void *cbmem_top_chipset(void)
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top = (uintptr_t)qemu_get_memory_size() * 1024;
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}
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if (CONFIG(BOARD_EMULATION_QEMU_X86_Q35)) {
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size_t smm_size;
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smm_region(&top, &smm_size);
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}
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return (void *)top;
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}
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@ -2,17 +2,21 @@ bootblock-y += bootblock.c
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romstage-y += ../qemu-i440fx/fw_cfg.c
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romstage-y += ../qemu-i440fx/memmap.c
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romstage-y += memmap.c
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postcar-y += ../qemu-i440fx/fw_cfg.c
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postcar-y += ../qemu-i440fx/memmap.c
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postcar-y += ../qemu-i440fx/exit_car.S
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postcar-y += memmap.c
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ramstage-y += ../qemu-i440fx/fw_cfg.c
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ramstage-y += ../qemu-i440fx/memmap.c
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ramstage-y += ../qemu-i440fx/northbridge.c
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ramstage-y += memmap.c
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verstage-$(CONFIG_CHROMEOS) += chromeos.c
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verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += memmap.c
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@ -0,0 +1,43 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#define __SIMPLE_DEVICE__
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <device/pci_ops.h>
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#include <mainboard/emulation/qemu-i440fx/memory.h>
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#include <mainboard/emulation/qemu-i440fx/fw_cfg.h>
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#define EXT_TSEG_MBYTES 0x50
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#define SMRAMC 0x9d
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#define G_SMRAME (1 << 3)
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#define D_LCK (1 << 4)
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#define D_CLS (1 << 5)
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#define D_OPEN (1 << 6)
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#define ESMRAMC 0x9e
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#define T_EN (1 << 0)
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#define TSEG_SZ_MASK (3 << 1)
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#define H_SMRAME (1 << 7)
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void smm_region(uintptr_t *start, size_t *size)
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{
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uint8_t esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC);
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switch ((esmramc & TSEG_SZ_MASK) >> 1) {
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case 0:
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*size = 1 * MiB;
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break;
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case 1:
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*size = 2 * MiB;
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break;
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case 2:
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*size = 8 * MiB;
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break;
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default:
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*size = pci_read_config16(PCI_DEV(0, 0, 0), EXT_TSEG_MBYTES) * MiB;
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}
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*start = qemu_get_memory_size() * KiB - *size;
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printk(BIOS_SPEW, "SMM_BASE: 0x%08lx, SMM_SIZE: %zu MiB\n", *start, *size / MiB);
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}
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