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soc/amd/picasso: Add UPDs for support eDP power sequence adjust 

Add UPDs for eDP power sequence adjust.

BUG=b:171954512
BRANCH=zork
TEST=Build, verify the parameter pass to picasso-fsp

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ic4bafd86ffb7804c4739f9d30beb67549b71d289
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This commit is contained in:
Chris Wang 2020-12-23 04:16:03 +08:00 committed by Patrick Georgi
parent 027b8b2ab9
commit 27b149c30b
1 changed files with 19 additions and 10 deletions
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29
src/vendorcode/amd/fsp/picasso/FspsUpd.h
View File

@ -40,16 +40,25 @@ typedef struct __packed {
/** Offset 0x0128**/ uint8_t gnb_ioapic_id;
/** Offset 0x0129**/ uint8_t fch_ioapic_id;
/** Offset 0x012A**/ uint8_t UnusedUpdSpace0[6];
/** Offset 0x0130**/ uint8_t unused4[16];
/** Offset 0x0140**/ uint8_t DpPhyOverride;
/** Offset 0x0141**/ uint16_t EDpPhySel;
/** Offset 0x0143**/ uint8_t EDpVersion;
/** Offset 0x0144**/ uint8_t EDpTableSize;
/** Offset 0x0145**/ uint8_t DpVsPemphLevel;
/** Offset 0x0146**/ uint16_t MarginDeemPh;
/** Offset 0x0148**/ uint8_t Deemph6db4;
/** Offset 0x0149**/ uint8_t BoostAdj;
/** Offset 0x014A**/ uint8_t UnusedUpdSpace1[6];
/** Offset 0x0130**/ uint8_t unused4;
/** Offset 0x0131**/ uint8_t DpPhyOverride;
/** Offset 0x0132**/ uint16_t EDpPhySel;
/** Offset 0x0134**/ uint8_t EDpVersion;
/** Offset 0x0135**/ uint8_t EDpTableSize;
/** Offset 0x0136**/ uint8_t DpVsPemphLevel;
/** Offset 0x0137**/ uint16_t MarginDeemPh;
/** Offset 0x0139**/ uint8_t Deemph6db4;
/** Offset 0x013A**/ uint8_t BoostAdj;
/** Offset 0x013B**/ uint16_t backlight_pwmhz;
/** Offset 0x013D**/ uint8_t pwron_digon_to_de;
/** Offset 0x013E**/ uint8_t pwron_de_to_varybl;
/** Offset 0x013F**/ uint8_t pwrdown_varybloff_to_de;
/** Offset 0x0140**/ uint8_t pwrdown_de_to_digoff;
/** Offset 0x0141**/ uint8_t pwroff_delay;
/** Offset 0x0142**/ uint8_t pwron_varybl_to_blon;
/** Offset 0x0143**/ uint8_t pwrdown_bloff_to_varybloff;
/** Offset 0x0144**/ uint8_t min_allowed_bl_level;
/** Offset 0x0145**/ uint8_t UnusedUpdSpace1[11];
/** Offset 0x0150**/ uint16_t UpdTerminator;
} FSP_S_CONFIG;