soc/amd: add DISABLE_KEYBOARD_RESET_PIN option

The KBRST_L pin will cause a reset when driven or pulled low even when
the GPIO mux is set to GPIO and not native function. So when you want to
use that pin as general purpose output the keyboard reset input
functionality needs to be disabled by selecting this option in the
board's Kconfig file to avoid causing a reset by writing a 0 to the
output level bit when it's configured as an output.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: I517ad551db9321f26afdba15d97ddb61be1f7d51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51757
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/cezanne/Kconfig

@@ -204,6 +204,14 @@ config DISABLE_SPI_FLASH_ROM_SHARING
 	  removes arbitration with board and assumes the chipset controls
 	  the SPI flash bus entirely.
 
+config DISABLE_KEYBOARD_RESET_PIN
+	bool
+	help
+	  Instruct the SoC to not use the state of GPIO_129 as keyboard reset
+	  signal. When this pin is used as GPIO and the keyboard reset
+	  functionality isn't disabled, configuring it as an output and driving
+	  it as 0 will cause a reset.
+
 menu "PSP Configuration Options"
 
 config AMD_FWM_POSITION_INDEX

src/soc/amd/cezanne/early_fch.c

@@ -52,6 +52,10 @@ void fch_pre_init(void)
 
 	if (CONFIG(AMD_SOC_CONSOLE_UART))
 		set_uart_config(CONFIG_UART_FOR_CONSOLE);
+
+	/* disable the keyboard reset function before mainboard GPIO setup */
+	if (CONFIG(DISABLE_KEYBOARD_RESET_PIN))
+		fch_disable_kb_rst();
 }
 
 /* After console init */

src/soc/amd/picasso/Kconfig

@@ -320,6 +320,14 @@ config DISABLE_SPI_FLASH_ROM_SHARING
 	  removes arbitration with board and assumes the chipset controls
 	  the SPI flash bus entirely.
 
+config DISABLE_KEYBOARD_RESET_PIN
+	bool
+	help
+	  Instruct the SoC to not use the state of GPIO_129 as keyboard reset
+	  signal. When this pin is used as GPIO and the keyboard reset
+	  functionality isn't disabled, configuring it as an output and driving
+	  it as 0 will cause a reset.
+
 config MAINBOARD_POWER_RESTORE
 	def_bool n
 	help

src/soc/amd/picasso/early_fch.c

@@ -62,6 +62,10 @@ void fch_pre_init(void)
 
 	if (CONFIG(AMD_SOC_CONSOLE_UART))
 		set_uart_config(CONFIG_UART_FOR_CONSOLE);
+
+	/* disable the keyboard reset function before mainboard GPIO setup */
+	if (CONFIG(DISABLE_KEYBOARD_RESET_PIN))
+		fch_disable_kb_rst();
 }
 
 /* After console init */

src/soc/amd/stoneyridge/Kconfig

@@ -371,6 +371,14 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 	int
 	default 133
 
+config DISABLE_KEYBOARD_RESET_PIN
+	bool
+	help
+	  Instruct the SoC to not use the state of GPIO_129 as keyboard reset
+	  signal. When this pin is used as GPIO and the keyboard reset
+	  functionality isn't disabled, configuring it as an output and driving
+	  it as 0 will cause a reset.
+
 config MAINBOARD_POWER_RESTORE
 	def_bool n
 	help

src/soc/amd/stoneyridge/southbridge.c

@@ -344,6 +344,10 @@ void bootblock_fch_early_init(void)
 
 	fch_enable_legacy_io();
 	enable_aoac_devices();
+
+	/* disable the keyboard reset function before mainboard GPIO setup */
+	if (CONFIG(DISABLE_KEYBOARD_RESET_PIN))
+		fch_disable_kb_rst();
 }
 
 /* After console init */