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soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbers 

Modify the FCH ACPI devices to query the PCI IRQ mapping registers for
their current IRQ numbers.

BUG=b:139429446, b:154756391
TEST=Boot trembyle and see that I2C and UART devices are finally
functional.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8f2035f74240ead4089ff4d503dfbeb447cf8de4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Raul E Rangel 2020-03-10 14:05:42 -06:00 committed by Patrick Georgi
parent 1761d33da6
commit 27b6b0ed72
2 changed files with 240 additions and 50 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
src/soc/amd/picasso/acpi/pcie.asl
View File

@ -16,6 +16,21 @@
PIRG, 0x00000008, /* Index 6: INTG */
PIRH, 0x00000008, /* Index 7: INTH */
Offset (0x62),
PGPI, 0x00000008, /* Index 0x62: GPIO */
Offset (0x70),
PI20, 0x00000008, /* Index 0x70: I2C0 */
PI21, 0x00000008, /* Index 0x71: I2C1 */
PI22, 0x00000008, /* Index 0x72: I2C2 */
PI23, 0x00000008, /* Index 0x73: I2C3 */
PUA0, 0x00000008, /* Index 0x74: UART0 */
PUA1, 0x00000008, /* Index 0x75: UART1 */
PI24, 0x00000008, /* Index 0x76: I2C4 */
PI25, 0x00000008, /* Index 0x77: I2C5 */
PUA2, 0x00000008, /* Index 0x78: UART2 */
PUA3, 0x00000008, /* Index 0x79: UART3 */
/* IO-APIC IRQs */
Offset (0x80),
IORA, 0x00000008, /* Index 0x80: INTA */
@ -26,6 +41,21 @@
IORF, 0x00000008, /* Index 0x85: INTF */
IORG, 0x00000008, /* Index 0x86: INTG */
IORH, 0x00000008, /* Index 0x87: INTH */
Offset (0xE2),
IGPI, 0x00000008, /* Index 0xE2: GPIO */
Offset (0xF0),
II20, 0x00000008, /* Index 0xF0: I2C0 */
II21, 0x00000008, /* Index 0xF1: I2C1 */
II22, 0x00000008, /* Index 0xF2: I2C2 */
II23, 0x00000008, /* Index 0xF3: I2C3 */
IUA0, 0x00000008, /* Index 0xF4: UART0 */
IUA1, 0x00000008, /* Index 0xF5: UART1 */
II24, 0x00000008, /* Index 0xF6: I2C4 */
II25, 0x00000008, /* Index 0xF7: I2C5 */
IUA2, 0x00000008, /* Index 0xF8: UART2 */
IUA3, 0x00000008, /* Index 0xF9: UART3 */
}
/* PCI Error control register */

218
src/soc/amd/picasso/acpi/sb_fch.asl
View File

@ -26,12 +26,30 @@ Device (GPIO)
Name (_UID, 0)
Name (_DDN, GPIO_DEVICE_DESC)
Name (_CRS, ResourceTemplate()
{
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
{ 7 }
Method (_CRS, 0) {
Name (RBUF, ResourceTemplate() {
Interrupt (
ResourceConsumer,
Level,
ActiveLow,
Exclusive, , , IRQR)
{ 0 }
Memory32Fixed (ReadWrite, 0xFED81500, 0x300)
})
CreateDWordField (RBUF, IRQR._INT, IRQN)
If (PMOD) {
IRQN = IGPI
} Else {
IRQN = PGPI
}
If (IRQN == 0x1f) {
Return (ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xFED81500, 0x300)
})
} Else {
Return (RBUF)
}
}
Method (_STA, 0x0, NotSerialized)
{
@ -43,12 +61,33 @@ Device (FUR0)
{
Name (_HID, "AMD0020")
Name (_UID, 0x0)
Name (_CRS, ResourceTemplate()
{
IRQ (Edge, ActiveHigh, Exclusive) { 10 }
Method (_CRS, 0) {
Name (RBUF, ResourceTemplate() {
Interrupt (
ResourceConsumer,
Edge,
ActiveHigh,
Exclusive, , , IRQR)
{ 0 }
Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000)
Memory32Fixed (ReadWrite, APU_DMAC0_BASE, 0x1000)
})
CreateDWordField (RBUF, IRQR._INT, IRQN)
If (PMOD) {
IRQN = IUA0
} Else {
IRQN = PUA0
}
If (IRQN == 0x1f) {
Return (ResourceTemplate() {
Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000)
Memory32Fixed (ReadWrite, APU_DMAC0_BASE, 0x1000)
})
} Else {
Return (RBUF)
}
}
Method (_STA, 0x0, NotSerialized)
{
Return (0x0F)
@ -58,28 +97,69 @@ Device (FUR0)
Device (FUR1) {
Name (_HID, "AMD0020")
Name (_UID, 0x1)
Name (_CRS, ResourceTemplate()
{
IRQ (Edge, ActiveHigh, Exclusive) { 11 }
Method (_CRS, 0) {
Name (RBUF, ResourceTemplate() {
Interrupt (
ResourceConsumer,
Edge,
ActiveHigh,
Exclusive, , , IRQR)
{ 0 }
Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000)
Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000)
})
CreateDWordField (RBUF, IRQR._INT, IRQN)
If (PMOD) {
IRQN = IUA1
} Else {
IRQN = PUA1
}
If (IRQN == 0x1f) {
Return (ResourceTemplate() {
Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000)
Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000)
})
} Else {
Return (RBUF)
}
}
Method (_STA, 0x0, NotSerialized)
{
Return (0x0F)
}
}
Device (FUR2)
{
Device (FUR2) {
Name (_HID, "AMD0020")
Name (_UID, 0x0)
Name (_CRS, ResourceTemplate()
{
IRQ (Edge, ActiveHigh, Exclusive) { 15 }
Name (_UID, 0x2)
Method (_CRS, 0) {
Name (RBUF, ResourceTemplate() {
Interrupt (
ResourceConsumer,
Edge,
ActiveHigh,
Exclusive, , , IRQR)
{ 0 }
Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000)
Memory32Fixed (ReadWrite, APU_DMAC2_BASE, 0x1000)
})
CreateDWordField (RBUF, IRQR._INT, IRQN)
If (PMOD) {
IRQN = IUA2
} Else {
IRQN = PUA2
}
If (IRQN == 0x1f) {
Return (ResourceTemplate() {
Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000)
Memory32Fixed (ReadWrite, APU_DMAC2_BASE, 0x1000)
})
} Else {
Return (RBUF)
}
}
Method (_STA, 0x0, NotSerialized)
{
Return (0x0F)
@ -88,13 +168,34 @@ Device (FUR2)
Device (FUR3) {
Name (_HID, "AMD0020")
Name (_UID, 0x1)
Name (_CRS, ResourceTemplate()
{
IRQ (Edge, ActiveHigh, Exclusive) { 5 }
Name (_UID, 0x3)
Method (_CRS, 0) {
Name (RBUF, ResourceTemplate() {
Interrupt (
ResourceConsumer,
Edge,
ActiveHigh,
Exclusive, , , IRQR)
{ 0 }
Memory32Fixed (ReadWrite, APU_UART3_BASE, 0x1000)
Memory32Fixed (ReadWrite, APU_DMAC3_BASE, 0x1000)
})
CreateDWordField (RBUF, IRQR._INT, IRQN)
If (PMOD) {
IRQN = IUA3
} Else {
IRQN = PUA3
}
If (IRQN == 0x1f) {
Return (ResourceTemplate() {
Memory32Fixed (ReadWrite, APU_UART3_BASE, 0x1000)
Memory32Fixed (ReadWrite, APU_DMAC3_BASE, 0x1000)
})
} Else {
Return (RBUF)
}
}
Method (_STA, 0x0, NotSerialized)
{
Return (0x0F)
@ -104,11 +205,30 @@ Device (FUR3) {
Device (I2C2) {
Name (_HID, "AMD0010")
Name (_UID, 0x2)
Name (_CRS, ResourceTemplate()
{
IRQ (Edge, ActiveHigh, Exclusive) { 4 }
Method (_CRS, 0) {
Name (RBUF, ResourceTemplate() {
Interrupt (
ResourceConsumer,
Edge,
ActiveHigh,
Exclusive, , , IRQR)
{ 0 }
Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000)
})
CreateDWordField (RBUF, IRQR._INT, IRQN)
If (PMOD) {
IRQN = II22
} Else {
IRQN = PI22
}
If (IRQN == 0x1f) {
Return (ResourceTemplate() {
Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000)
})
} Else {
Return (RBUF)
}
}
Method (_STA, 0x0, NotSerialized)
{
@ -120,24 +240,64 @@ Device (I2C3)
{
Name (_HID, "AMD0010")
Name (_UID, 0x3)
Name (_CRS, ResourceTemplate() {
IRQ (Edge, ActiveHigh, Exclusive) { 6 }
Method (_CRS, 0) {
Name (RBUF, ResourceTemplate() {
Interrupt (
ResourceConsumer,
Edge,
ActiveHigh,
Exclusive, , , IRQR)
{ 0 }
Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000)
})
CreateDWordField (RBUF, IRQR._INT, IRQN)
If (PMOD) {
IRQN = II23
} Else {
IRQN = PI23
}
If (IRQN == 0x1f) {
Return (ResourceTemplate() {
Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000)
})
} Else {
Return (RBUF)
}
}
Method (_STA, 0x0, NotSerialized)
{
Return (0x0F)
}
}
Device (I2C4)
{
Device (I2C4) {
Name (_HID, "AMD0010")
Name (_UID, 0x4)
Name (_CRS, ResourceTemplate() {
IRQ (Edge, ActiveHigh, Exclusive) { 14 }
Method (_CRS, 0) {
Name (RBUF, ResourceTemplate() {
Interrupt (
ResourceConsumer,
Edge,
ActiveHigh,
Exclusive, , , IRQR)
{ 0 }
Memory32Fixed (ReadWrite, APU_I2C4_BASE, 0x1000)
})
CreateDWordField (RBUF, IRQR._INT, IRQN)
If (PMOD) {
IRQN = II24
} Else {
IRQN = PI24
}
If (IRQN == 0x1f) {
Return (ResourceTemplate() {
Memory32Fixed (ReadWrite, APU_I2C4_BASE, 0x1000)
})
} Else {
Return (RBUF)
}
}
Method (_STA, 0x0, NotSerialized)
{
Return (0x0F)