From 27ba085334d1482c08b5fd9e628a0f11a0fd9202 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 29 Sep 2020 11:52:57 +0200 Subject: [PATCH] mb/emulation/q35: Define pm_acpi_smi_cmd_port The X86 Qemu targets use the AMD64 SMM save state, but unlike most AMD CPU's the PM ACPI SMI port is not configurable and uses the Intel default APM_CNT, 0xb2 port. This will be used by the common save state handler. Change-Id: Ifee9476f628a2df710fb4340ce6a19b008df1033 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/45814 Reviewed-by: Patrick Rudolph Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/emulation/qemu-q35/Makefile.inc | 2 ++ src/mainboard/emulation/qemu-q35/smi.c | 9 +++++++++ 2 files changed, 11 insertions(+) create mode 100644 src/mainboard/emulation/qemu-q35/smi.c diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index e142d4d5c1..ddcf6da062 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -14,3 +14,5 @@ ramstage-y += ../qemu-i440fx/northbridge.c verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smi.c diff --git a/src/mainboard/emulation/qemu-q35/smi.c b/src/mainboard/emulation/qemu-q35/smi.c new file mode 100644 index 0000000000..5d8d48295c --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/smi.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* The X86 qemu target uses AMD64 save states but the APM port is not configurable. */ +uint16_t pm_acpi_smi_cmd_port(void) +{ + return APM_CNT; +}