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cpu/amd/model_10xxx: Do not initialize SMM memory if SMM is disabled 

In the wake of the recent Intel "Memoy Sinkhole" exploit a code review
of the AMD SMM code was undertaken.  While native Family 10h support
does not appear to be affected by the same SMM flaw, it also does not
require SMM to function.  Therefore, the SMM memory range initialization
should only be executed if SMM will be used on the target platform.

Change-Id: I6531908a7724933e4ba5a2bbefeb89356197e8fd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11211
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Timothy Pearson 2015-08-12 11:19:10 -05:00 committed by Alexandru Gagniuc
parent e3260ec29a
commit 27baa32fbe
1 changed files with 24 additions and 8 deletions
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16
src/cpu/amd/model_10xxx/model_10xxx_init.c
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@ -99,6 +99,9 @@ static void model_10xxx_init(device_t dev)
msr.hi &= ~(1 << (35-32));
wrmsr(BU_CFG2_MSR, msr);
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
printk(BIOS_DEBUG, "Initializing SMM ASeg memory\n");
/* Set SMM base address for this CPU */
msr = rdmsr(SMM_BASE_MSR);
msr.lo = SMM_BASE - (lapicid() * 0x400);
@ -108,6 +111,19 @@ static void model_10xxx_init(device_t dev)
msr = rdmsr(SMM_MASK_MSR);
msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
wrmsr(SMM_MASK_MSR, msr);
} else {
printk(BIOS_DEBUG, "Disabling SMM ASeg memory\n");
/* Set SMM base address for this CPU */
msr = rdmsr(SMM_BASE_MSR);
msr.lo = SMM_BASE - (lapicid() * 0x400);
wrmsr(SMM_BASE_MSR, msr);
/* Disable the SMM memory window */
msr.hi = 0x0;
msr.lo = 0x0;
wrmsr(SMM_MASK_MSR, msr);
}
/* Set SMMLOCK to avoid exploits messing with SMM */
msr = rdmsr(HWCR_MSR);