soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache
Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I8777b0c8471fe17ffffdcb6ad5b7c00fb1d35db1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52925 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -35,6 +35,7 @@ romstage-y += ../common/mt6359p.c mt6359p.c
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ramstage-y += emi.c
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ramstage-y += ../common/flash_controller.c
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ramstage-y += ../common/gpio.c gpio.c
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ramstage-y += ../common/mmu_operations.c mmu_operations.c
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ramstage-y += ../common/mtcmos.c mtcmos.c
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ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
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ramstage-y += soc.c
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@ -0,0 +1,31 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/mmio.h>
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#include <soc/mcucfg.h>
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#include <soc/mmu_operations.h>
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#include <soc/symbols.h>
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DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9)
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DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8)
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void mtk_soc_disable_l2c_sram(void)
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{
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unsigned long v;
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SET32_BITFIELDS(&mt8195_mcucfg->mp0_cluster_cfg0,
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MP0_CLUSTER_CFG0_L3_SHARE_EN, 0);
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dsb();
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__asm__ volatile ("mrs %0, S3_0_C15_C3_5" : "=r" (v));
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v |= (0xf << 4);
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__asm__ volatile ("msr S3_0_C15_C3_5, %0" : : "r" (v));
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dsb();
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do {
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__asm__ volatile ("mrs %0, S3_0_C15_C3_7" : "=r" (v));
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} while (((v >> 0x4) & 0xf) != 0xf);
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SET32_BITFIELDS(&mt8195_mcucfg->mp0_cluster_cfg0,
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MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0);
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dsb();
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}
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@ -2,6 +2,7 @@
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#include <device/device.h>
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#include <soc/emi.h>
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#include <soc/mmu_operations.h>
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#include <symbols.h>
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static void soc_read_resources(struct device *dev)
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@ -11,6 +12,7 @@ static void soc_read_resources(struct device *dev)
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static void soc_init(struct device *dev)
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{
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mtk_mmu_disable_l2c_sram();
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}
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static struct device_operations soc_ops = {
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